FAULT MODELING AND SIMULATION TOOLS FOR i_DDT TESTING

Scott Anderson Thomas

A dissertation submitted to the faculty of

The University of North Carolina at Charlotte

in partial fulfillment of the requirements

for the degree of Doctor of Philosophy in the

Department of Electrical and Computer Engineering

Charlotte

2004

Approved by:

______________________________

Dr. Rafic Z. Makki

______________________________

Dr. Yogendra P. Kakad

______________________________

Dr. Farid M. Tranjan

______________________________

Dr. Thomas P. Weldon

______________________________

Dr. David M. Wu

______________________________

Dr. John L. Daniels

Scott Anderson Thomas

ABSTRACT

SCOTT ANDERSON THOMAS. Fault Modeling and Simulation Tools

for iDDT Testing. (Under the direction of DR. RAFIC Z. MAKKI)

This dissertation presents both tools and information to advance the field of electronics testing, specifically in the relatively new area of iDDT testing. As modern technology allows increasing complexity of electronic circuits, the testing methods are tasked to keep pace with the phenomenal growth. While the traditional test methods are still being used, it is clear that additional test strategies are necessary to increase the reliability of products as well as decrease the cost of testing.

The first part of this work documents the creation of several Computer Aided Design (CAD) tools that not only characterize and analyze electronic circuits at the gate level, but also take the transistor level faults into account. To accomplish this goal, the main CAD program requires a library of faults. This library of faults will map the transistor level defects into gate level circuits. Additionally, an efficient set of test patterns is required to stimulate the circuit inputs. Therefore, another CAD program presented here analyzes a logic circuit and gives an appropriate set of test vectors. The main CAD tool uses all of the information to characterize the operation of the suspect circuit.

The second part of this work provides valuable measurement and fault model information. An overview of the laboratory equipment and general guidelines for measurements of this type are presented. Also presented are the PC boards which have been designed specifically to reduce interference. Finally, the measured results of circuit defects in several fabricated devices are shown. Further, these circuits are simulated with an emphasis on matching the measured responses as closely as possible. The goal of

these experiments is to have a deep understanding of measured data and accurate fault models. The ultimate goal of this dissertation is to present the results from these experiments in conjunction with the CAD tools described above to provide tools and information to aid the advance of electronics testing using the iDDT method.

ACKNOWLEDGEMENTS

Thanks are extended to the following for their cooperation and assistance in the development of this project:

Doctor Rafic Makki for driving this research and providing financial support.

The _iDDT student research team for their dedication and hard work.

Doctor Kakad for the true support and encouragement. Doctor Sharer for paving the way for others to follow. Doctors Weldon and Daniels for attending not only the proposal, but also the defense. Doctors Tranjan, Wu, and Binkley for the support and encouragement.

The William States Lee College of Engineering, the Department of Electrical and Computer Engineering, the C.C. Cameron Applied Research Center, and the UNC Charlotte Graduate School for being so devoted to education.

The National Science Foundation (NSF) and Defense Advanced Research Projects Agency (DARPA) for the funding of this as well as many other projects. Their generous support has underscored the fact that academics and research provide valuable contributions.

My family, especially my parents Doctor John and Jan Thomas, for their patience and support throughout my lengthy educational career.

My friends and associates for their various levels of support. Although it would be hard to make a complete list, the examples in Chapter 2 of this dissertation attempt to do so by naming the nodes and gates of the comprehensive example with familiar names. Apologies are offered for any accidental exclusion. Each mention is a sincere nod of appreciation and recognition.

TABLE OF CONTENTS

CHAPTER 1: FABRICATION AND TESTING ELECTRONIC CIRCUITS 1

1.1 Fabrication 1

1.2 i_DDQ Testing 3

1.3 i_DDT Testing 5

CHAPTER 2: THE TOGGLE TEST PATTERN GENERATION TOOL 8

2.1 Toggle Algorithm User Options 11

2.2 Toggle Algorithm Data Processing 13

2.2.1 The Brute Force Method 14

2.2.2 The Toggle Target Method 17

2.3 Displaying and Interpreting the Results 25

2.4 Toggle Algorithm Examples 26

CHAPTER 3: MAPPER COMPUTER AIDED DESIGN TOOL 37

3.1 Mapper CAD Algorithm User Options 39

3.2 Analysis of a Defective Circuit 41

3.3 Analysis of a Defect-free Circuit 44

3.4 The Library of Gates 45

3.5 Displaying and Interpreting the Results 48

3.6 Mapper CAD Algorithm Examples 49

3.7 Mapper CAD with Laboratory Measurements 54

CHAPTER 4: DATA MEAUSRMENTS 61

4.1 Measurement Challenges 62

4.2 Laboratory Equipment 64

4.3 Measured Data Summary 67

CHAPTER 5: CONCLUSIONS AND FUTURE WORK 114

REFERENCES 118

APPENDIX A: MAPPER CAD LIBRARY 123

APPENDIX B: MAPPER CAD ALGORITHM TEST SOFTWARE 145

APPENDIX C: SPICE FILE SAMPLE 160

CHAPTER 1: FABRICATION AND TESTING ELECTRONIC CIRCUITS

The evolution of the electronics industry has profoundly impacted virtually every aspect of modern life. In a relatively short time, a mere matter of decades, the integrated circuit has developed from a large piece of silicon containing two transistors to a small sliver of material containing millions of transistors. Complimentary Metal Oxide Semiconductors (CMOS) is currently the most popular logic design technology used today. However, the trends in fabrication undoubtedly will give way to a new generation of circuit technology [1], [2]. The phenomenal growth of complicated circuits has lead to powerful systems on chips, but has also caused the Herculean task of testing the vast number of components.

1.1 Fabrication

Since the end goal of a quality product is shared by both the consumer and the manufacturer, testing can be considered the final step in the manufacturing process. Nevertheless, the initial steps of circuit fabrication are just as impressive. To produce a wafer, silicon with a purity of less than one part per billion is heated to the melting point of 1420°C in either an atmosphere of inert gas or a vacuum. A seed crystal is dipped and slowly withdrawn so that silicon “freezes” to form a silicon ingot. The temperature and the speed of the pull determine the diameter of the ingot. The next step is to trim and grind the ingot to obtain a uniform diameter and orientation flat or notch. The silicon is then sliced, polished and cleaned to form a bare silicon wafer [3].

Many copies of the Integrated Circuit (IC) are fabricated on a single silicon wafer. This is referred to as “packing” the wafer and involves some strategy [4], [5]. The circuits themselves are built up in layers. Therefore the process involves many different steps. The Diffusion process involves heating the wafer to approximately 1000°C and planting dopant impurities into the material to modify its electrical characteristics. Also available in some cases as an alternative to deposition diffusion is Ion Implantation. This involves bombarding the wafer with ions that have been accelerated through a voltage of anywhere from 20 to 250 kV. In the Oxidation process, oxygen reacts with the silicon to form a layer of silicon dioxide. Various temperatures and pressures can be used to control the thickness of this layer.

Photolithography is a multi-step process that involves using light sensitive chemicals to create the intricate patterns of the circuit. Chemical-vapor deposition adds thin film layers on the wafer, including the special case of the epitaxial layer which consists of a deposited layer in single-crystal form. The Metalization process adds thin film metal conductors to the circuit. Once the circuit fabrication is completed, the devices are cut apart and individually packaged to make the components used in the electronics industry.

Obviously this summary on the fabrication process is brief. Each of the steps can be quite involved and unfortunately vulnerable to catastrophic mistakes. The fabrication process is complicated and requires expensive equipment, valuable time, and many resources such as energy, water, and chemicals. In practice, every aspect of the production line, from the material used to the physical layout of the facility is considered. Any small impact to any aspect of inventory, production costs, or the product itself is considered a serious matters in this highly competitive business [6] – [10].

With today's technology, the integrated circuit is becoming smaller and smaller, almost to the point of exceeding limits which researchers once thought impossible. Manufacturers prefer tiny circuits for several reasons: lower power, faster speeds, and lower cost. However in many ways the highest cost of shrinking these circuits is not paid for with money, but with the time and complexity required to assure the reliability of these circuits.

As a circuit size is decreased, the effects of a minor defect such as a dust particle on the silicon wafer becomes critically important. A small defect that used to be inconsequential can cause a complete logic failure. The shrinking size lowers the margin for error. Also the smaller size allows more and more devices per chip. Therefore, it would take that much more time to fully test the devices. Since memory devices can now have millions of transistors, even the fastest test can take a surprising amount of time. For example, testing a 1MB memory chip at the rate of one bit per nanosecond (that is, testing 1000 bits each second) would still take over 2 hours to fully test the device.

1.2 i_DDQ Testing

Once the huge investments have been made to fabricate a chip, the testing procedure becomes a critical step. The problem at this juncture is deciding which testing process is appropriate. The use of i_DDQ testing methods has been used for decades. This involves measuring the current flowing into the device under static input conditions. Figure 1 shows the generic configuration of the power supply, the connecting lines, and

Figure 1 The generic test setup showing the power supply, the connecting lines, the device under test, and the i_DD current flow.

the device under test (DUT). The addition of the “Q” defines the current to be “quiescent” or steady state.

Of course, the i_DDQ test method does involve some level of planning. Effective test patterns that compliment the circuit are required. The type of device can determine the effectiveness of i_DDQ test. For example, CMOS random access memory (RAM) chips are good candidates for current testing. Some other types of circuits can include internal circuitry to facilitate the i_DDQ measurements. One advantage of adding an internal sensor is the ability for the scalable test circuitry to follow the design through shrinking technology and reduce the effects of process variations [11]-[17].

Even with internal designs, external equipment is often required. This adds another level of time and equipment to the fabrication and testing process. One disadvantage of i_DDQ testing is the fact that it does take a relatively long time to test a circuit for faults. Studies have shown that i_DDQ testing does provide some fault coverage, but some have predicted that i_DDQ tests may soon become obsolete. In any event, a single test method can not provide the complete answer. The conclusion is clear that several test methods are needed to provide full fault coverage [18]-[22].

1.3 i_DDT Testing

The natural extension of i_DDQ testing is i_DDT testing. This test method observes the same parameter used for i_DDQ testing, but does so under different circumstances. Instead of using the quiescent current levels, i_DDT testing focuses on the transient current pulses created when the inputs to a circuit are switched. Figure 2 shows the generic test setup for this type of dynamic power supply current measurements. These active measurements share some of the same strengths and weaknesses of the static current measurements. For example, the measurements can be made using external equipment, or by integrating some sort of sensor, or both. However, the i_DDT test method is better suited to find some types of defects than its i_DDQ counterpart. In particular, the open defects that are not easily discovered with i_DDQ tests are known to cause delay faults that are easily seen with i_DDT [23]-[26].

Many studies have shown the ability to detect defects in RAMs and other CMOS circuits. Even though the switching input levels cause an environment that is inherently noisy, efforts have been made to eliminate or reduce these unwanted signals. Some have had success using inductive sensors such as a coil around the Vdd line to minimize the effects of measuring the circuit. Another way to minimize the effects of noise is to take ratio measurements of defective and the defect-free circuits. This method can be extended to predict other circuit parameters such as the critical path delay through a

Figure 2 The generic test setup showing the power supply, the connecting lines, the device under test, and the i_DDT current flow. In this type of configuration, the changing inputs are expected to produce fluctuations in the current flowing through the Vdd line.

circuit. Although this testing method is admittedly noisy, it does provide fault coverage in less time than previous current testing methods [27]-[31].

Even with all these studies, i_DDT testing is still in its infancy. Some sections of the semiconductor industry are stuck in an older way of thinking, and are suspicious of this new test method. The cost of equipment, additional training, and the time spent towards another step in their fabrication process continue to bolster the reluctance to adopting this testing method. Supporting this position is the fact that the i_DDT currents are heavily dependent on the size of the technology. As the increasing technology allows smaller and smaller circuit, the testing methods are challenged to keep pace [32], [33].

The main goals of this dissertation are to present an algorithm for a new computer aided design (CAD) tool and to present several informative examples that compare simulated i_DDT data with measured i_DDT data. The CAD tool can be used by industry and educators to provide insight and aid the design of future electronic circuits. With the available amount of simulated i_DDT data far outweighing the available amount of measured i_DDT data, the examples provide some previously unseen i_DDT circuits various stages of design. The technology used in these examples is the 0.5-micron process. The unique tools and novel information presented in this dissertation should facilitate the advancement of the i_DDT test method.

CHAPTER 2: THE TOGGLE TEST PATTERN GENERATION TOOL

Because i_DDT is such a difficult parameter to measure, it is important to limit any interference and to minimize all potential noise sources. These sources include the activation of other gates in the circuit under test. Even if other parts of the circuit are functioning properly and therefore providing an expected pulse, the resulting current can mask the effects of the gates that are being analyzed at that particular time. Obviously, finding an effective and efficient method for targeting a particular gate within a circuit is paramount to the success of i_DDT measurements on combinational circuits.

For small circuits, the designer can easily choose the inputs required to sensitize a path to a target gate while at the same time desensitizing the surrounding gates. The human brain is an unrivaled analog computer that can handle the logical aspects of circuit analysis. It also possesses the unique ability to process data using intuitive components unmatched by any machine. This intuition is necessary for an understanding of the implications of setting a node to a particular value and affecting the other parts of the circuit. In other words, the designer has the advantage of understanding the big picture and easily backtracking one or two decisions to make a better choice. However for larger circuits on the scale used in most practical applications, the designs become too complex and the node assignments become too time-consuming to accomplish by hand. The solution is to create and use tools that facilitate the process of circuit analysis.

Test patterns represent the inputs used to check an electronic circuit for errors and defects. An error happens when a logical mistake is introduced into the circuit. For example, a designer could have mistakenly used an OR gate in place of an AND gate. This error would be detected by applying the test pattern “01” and getting a high output when a low is expected. A physical defect can also change the expected output. If a trace on the circuit accidentally connects to the ground line the output could remain low regardless of any test pattern applied to the inputs. The test patterns need to provide an acceptable level of coverage, and also be efficient enough to warrant their cost in time and resources.

For a test pattern to be effective and efficient, it must be designed with the circuit and the targeted defects in mind. Many different automatic test pattern generation (ATPG) tools exist. The selection of the tool depends on its strengths and weaknesses to provide best available test patterns for a particular circuit. For example, an ATPG tool that provides the best test pattern for random access memory (RAM) chips does not necessarily provide the best test pattern for field programmable gate arrays (FPGA). Similarly, a tool that produces an efficient test pattern for detecting delay faults in a circuit does not necessarily produce the best pattern to detect stuck-at faults [34] – [41].

This chapter presents the description of an algorithm that will provide the best test patterns necessary to focus on a target gate, sensitize the smallest path to that gate, and desensitize the surrounding gates. The algorithm will provide the ability to switch any gate in a combinational circuit while at the same time switching the absolute minimum number of adjacent gates. When summarized in a single sentence, this sounds like a fairly simple task. However the truth is that unseen problems arise, especially when the algorithm must be flexible enough to handle the virtually infinite combinations of circuit connections.

The analysis of an algorithm is a cyclic process of analyzing, estimating, and refining until the desired level of detail is reached. The main three steps in the general analysis include the characterization of data, the abstract operations, and the numerical step count. Like many algorithms, the “Toggle” algorithm presented here is highly dependent on the data. The abstract operations used to process the data are detailed below. Using the number of nodes as the primary parameter, the running time is expressed in terms of N. The running time, or complexity, is not constant in the Toggle algorithm since increasing the number of nodes increases the computational time. However it is neither a linear progression nor an exponential process. In this case the complexity is proportional to the logarithmic function, log N. This Toggle algorithm solves a problem in NP, namely the existence of an efficient set of test vectors. Obviously, the algorithm would greatly benefit from a non-deterministic approach. However the fact that the Toggle can be executed successfully on conventional machines would indicate that it is NP-complete. This is no surprise because of the large number of interesting practical problems that share this characteristic [42].

It is important to realize that the Toggle algorithm represents the blueprint of the actual computer program. It explains the steps and the thought processes that guide the actions of the processor, but does not dictate the actual computer code. The following steps can be implemented in almost any computer language. However programming guidelines are given where appropriate to provide an insight to the practical use of the algorithm in creating a viable computer program.

2.1 Toggle Algorithm User Options

For the Toggle algorithm to be useful, it should provide some sort of menu for the user to navigate. This interaction allows the user to see the working file, display certain properties of the working file, or change the data. It also allows a choice in the way the information is processed. Figure 3 shows the high level overview of the Toggle algorithm. Notice that the first steps involve reading the input data and processing it to find the inputs. Of course the information file must be read at the beginning, but finding the inputs can also be included at this point for two reasons. First, finding the inputs is required by the algorithm, no matter which method is used to process the data. Second, the process is transparent to the user. Simply finding the inputs does not mean that it displays them to the user who may not be interested in the inputs at this point. Displaying these inputs is an option given in the next step of the process.

Finding the inputs to the circuit while reading in the circuit does allow for some early error detection. If there is some problem with the data file, it is possible that it will be discovered here and not later in the process. In our case, the circuit is represented in a text netlist file. The gates are numbered in order, and contain information including their logic function, their output node, and their input node(s). Since many different netlist protocols exist, the algorithm must be implemented in a way that is flexible enough to read in one or more of the generic forms. Most netlist formats contain similar information. In fact, the netlist code must contain at least enough information to completely represent the circuit. Most formats strictly adhere to a particular structure that is defined by the type of netlist. Luckily, it is a fairly simple task to reorganize one text file netlist and convert it into another.

Figure 3 The high level overview of the complete “Toggle” program.

An additional subprocedure can be written to allow the user to choose which type of netlist to use. Alternately, the subprocedure can attempt to recognize the type of netlist by comparing the text file to some expandable library of known netlist types. This option provides for a “smarter”, more powerful program, but introduces another point of failure. Attention should be given to error handling at this stage. The code should be able to handle events such as “File not found” and “Error reading file” without completely crashing. In our case the errors listed above would cause the error code to display, and then restart the program automatically. This gives the user another chance to input the correct file data.

Once the information has been entered and the inputs have been found, the user is able to choose which option to perform. The “Help” option can give a brief explanation of the program and the different options. To make sure that the netlist file contains the data expected by the user, the options of displaying the file contents, displaying the output nodes, and (by using the information found earlier) displaying the primary inputs are all presented as choices. It is convenient to allow another data file to be read from this point.

When implementing this algorithm in code, it should be clear that only the “Help”, the “Read data file”, and the “End” options are allowed from the start up condition. The algorithm can not run the option to find the primary inputs unless a working netlist file has been designated. Although this sounds obvious to the user, it must be actively addressed in the computer code. Once a working file has been set, the other options are available. In our case, all options were presented in a menu, and only those options available at that particular time were marked with an asterisk, *. This method of locking out some functions will become important at later steps in the algorithm, mainly due to the fact that large input values may rule out the practical use of some options.

2.2 Toggle Algorithm Data Processing

Once the user successfully reads in the netlist data file, one of two methods can be selected to process the information. Both methods provide the equivalent information, but do so using entirely different methods. Of course the user may have the option of running both methods on the same circuit to verify the results. However it is important to note that the results of the different methods are only guaranteed to agree in the number of the gates changing, and not the exact paths. For example, Figure 4 shows a simple logic circuit. Gate 3 can be toggled by using input A as part of the toggle path (shown highlighted in Figure 4 (a), or by using input C shown in Figure 4 (b) -- assuming that the other inputs are properly set to sensitize the particular toggle path. Either case will cause the targeted gate (Gate 3) to switch, and will do so by switching only one other gate (either Gate 1 or Gate 2, but not both).

2.2.1 The Brute Force Method

The first method option used in the Toggle algorithm is the “brute force” method. It finds the resulting logic values of every node for each combination of primary inputs. It keeps track of this information, and seeks a set of vectors that toggle the target gate with a minimum number of incidental switches from the surrounding gates. As one might imagine, a great deal of information is created using this brute force method. For n inputs, there will be 2ⁿ input combinations. Compounding the problem is the fact that this number then must be multiplied by the number of individual nodes in the circuit to get the final tally of entries needed in the matrix used to store the information. It is important to note that the total number of gates is not the limiting factor. The number of primary inputs should be the main consideration when using brute force. With this coded Toggle program, circuits with 10 or less primary inputs can be found with the brute force method. Obviously some programming tricks are needed to work around this excessive information problem.

The main trick used in this implementation is to store the information in text strings instead of storing each node value in its own array entry. Table 1 shows a sample array of typical node values. Table 2 shows the same information in a compact form.

Figure 4 (a) and 4 (b) Different “Toggle” paths that switch the same target gate. Although the paths traverse different gates, they are essentially equivalent since they both toggle gate 3 and toggle only one other gate.

Using this compression scheme the data manipulation becomes very cumbersome, but does allow extra variables to be used. Since the number of inputs and the number of gates are both constant, this string compression only needs to store the assigned values, 1 or 0. There is no need to identify the variable name as long as the assigned order of inputs and outputs is known and used consistently. This turns out to be a great advantage that becomes apparent in the later sections of the algorithm.

Table 1 Sample node array with single node entries.

Input 1	Input 2	Input 3	Input 4	Input 5	Input 6	Output 1	Output 2	Output 3
0	0	0	0	0	0	0	1	0
0	0	0	0	0	1	1	1	0
0	0	0	0	1	0	1	1	0
0	0	0	0	1	1	1	0	0
0	0	0	1	0	0	1	0	1
		…					…
1	1	1	1	1	1	1	0	1

Table 2 Sample node array with compressed node entries.

Inputs	Outputs
000000	010
000001	110
000010	110
000011	100
000100	101
…	…
111111	101

The price of this compression is not only the complex computer code, but also the fractional increase of processor time. Instead of comparing two variables directly, the variables must be found within a string and then assigned to some temporary variable before they can be used for comparisons. Another example of this is the way the input vectors are applied and increased in binary. Since the numbers are stored as strings, they must be picked out individually and then processed. This is certainly an inefficient use of time, but gives an enormous memory space advantage.

Figure 5 shows the brute force section of the Toggle algorithm. The first step is to assign the primary inputs. The logical choice is to pick all zeros. The next step is to sift these values through the circuit. As previously mentioned, this inspection is an easy task for a human, but a bit more difficult for the computer. It is accomplished by poling each gate and paying special attention to the inputs. If all of the inputs have been assigned a value but the output has not, then the inputs and the function of the gate are used to determine the state of the output.

Once the state of the output has been determined, the algorithm must take care of the bookkeeping by searching through each node and updating every occurrence with the variable in question. This process continues until all nodes in the circuit have been assigned a value. With all the information from that particular input vector stored in memory for later comparison, the algorithm moves on to the next input vector until all of the input vectors have been examined.

The next step is to sort through all of the internal nodes and the observable outputs to count the number of switching gates between each of the input vectors. It is important to note that one can not assume a 0 or 1 state for comparison on the output. Therefore the output of the first gate must be read and used as a base. Of course, this continues until the last input vector has been compared to all of the others. The output of this brute force section of the algorithm is the gate number, the best vector which toggles that gate, the number of gates switching (including the target gate itself), and the number of primary inputs changing between the two input vectors.

2.2.2 The Toggle Target Method

The target section of the Toggle algorithm is the workhorse of the program. This method chooses a set of test patterns that meet the same criteria set forth in the brute force section of the algorithm, but does so in an entirely different way. The primary idea is to pick a gate and sensitize at path to it. A secondary concern is to desensitize the gates that fan out from the target gate, as well as the gates that fan out from the devices that

Figure 5 The “Brute Force” section of the Toggle algorithm.

comprise the toggle path. This sounds simple enough, however there are numerous pitfalls along this journey. Figure 6 shows the Target section of the Toggle algorithm. Even in this simplified form, it is much more complicated than all the other sections combined.

One reason for the complicated nature of the Target section of the Toggle algorithm is the fact that it must be generic. In other words, it must be flexible enough to handle NAND gates that have 2 inputs, 3 inputs, or 4 inputs. This is true for the target gate, as well as all of the other gates that fan out from the toggle path. The computer code based on this algorithm must adapt to the circuit without any help from the user. This is no small task.

The first step in this difficult task is to initialize the primary input array, to some neutral value. It is not necessary to use all zeros or ones, as will be shown below. Since the primary inputs have already been found, it is only necessary to initialize their values. Next, determine the target gate number. Once the target gate has been determined, its inputs are examined to see if they are all primary inputs. Having all primary inputs

greatly simplifies this part of the algorithm since the gate can be accessed directly and the complicated procedure to map the toggle path is not necessary.

However if any input to the gate is at least one level deep into the circuit, it is necessary to set up and initialize a working array. This array initially contains the inputs to the target gate. These inputs are then compared to the other output nodes in the circuit. If a match exists, then the code must work backwards to find the number of inputs to that gate, for example n. Then the code must add n-1 entries to the working array, being sure to add the gate identifier to each of the entries. To make it easier to keep track of the current gate under investigation, the last gate identifier is stored in the working array. Keep in mind that this procedure also uses the string compression method used in the brute force part of the algorithm. In fact, the compression is crucial in this section since every possible path to the target gate must be investigated, and every node along these paths must be assigned a value (and therefore stored in the array). This backstep procedure is completed when all the input paths reaching the target gate are backtracked to their corresponding primary inputs.

A = Initialize primary array to neutral character, “+”.

B = Get target gate number and confirm with inputs and function.

C = Check to see if all inputs are primary.

D = Are all inputs primary?

E = Skip toggle path section of algorithm.

F = Initialize the working array.

G = Call Backstep procedure.

H = Find the number of inputs to the gate.

I = Copy the array entry n-1 times to increase the array size.

J = Keep the last node name as a separate array entry.

K = Check to see if the last node names are all primary inputs.

L = Are all last node names primary inputs?

M = Recall the Backstep procedure.

N = (Array now contains the steps to target gate) Sort to find the shortest path.

O = Find the number of steps in the smallest path.

P = Find the number of smallest paths.

Q = Set the top of the sorted array as the toggle variable.

R = Sensitize the gates along the toggle path.

S = Save the values in the working array if possible (if they are primary inputs).

T = Check to see if all values saved are primary inputs.

U = Find the gates AFTER the target gate.

V = Are all inputs to the gate primary inputs?

W = Look for fanouts from the toggle path.

X = Is there at least one fanout branch?

Y = Desensitize the gates common to the toggle path.

Z = Add new values for primary inputs to the working array.

AA = Do the new values clash with previous values?

AB = Display clash warning.

AC = Display input vectors and END.

Figure 6 The Target section of the Toggle Algorithm.

Getting the backstep part of the algorithm to work in computer code is a complicated task. As mentioned previously, this algorithm must be generic and work for gates with any number of inputs. Therefore, the programming can not repeat itself using preset “for” loops, such as “FOR x=1 TO 2” or “FOR (x=1, x<3, x++)”. The depth of the circuit is also an unknown variable. Therefore, the job of finding one gate path and then reverse backtracking (essentially moving forward in the circuit) to find the next path while keeping track of which nodes have been fully completed and which nodes are partially completed can grow to intimidating proportions. The trick in this case is to make the backstep procedure recursive. Therefore, the oversimplified explanation is to seed the working array with the target gate, call “backstep” once, and allow it to call itself until it has found all the paths from the target gate back to the primary inputs.

At this point in the process, the array is now filled with paths that lead from the target gate back to the primary inputs. No values have been assigned at this point, but the paths have been identified. Before assigning values to the paths, it is necessary to determine which of these paths is the best candidate to be the toggle path. Since the goal is to toggle the target gate with the least number of incidental gates, the obvious choice is to pick the shortest path. Using a variation of the bubble sort, bring the smallest path (or paths) to the top of the array. The path at the top of the array is now defined as the “toggle path”.

Since the toggle path is now clearly defined, the number of gates along the path is now known. This gives the number of incidental gates that will have to switch as the target gate is toggled. It is also a straightforward task to count the number of paths that have the same number of gates as the toggle path, since they are all listed in ascending order based on length. These other paths can be used as the toggle path (without increasing the number of incidental gate switches) if it is later determined that they will provide better results.

Working with the top path as the toggle path, it can be determined which primary input must be switched to toggle the target gate. However for this signal to reach the target gate, the toggle path must now be sensitized. To do this, each of the paths (excluding the toggle path) must be assigned logic values. These values depend on the function of the gate. For example the AND function requires a 1 on the other inputs, while the OR function requires a 0. Once all paths in this array have been completed, the target gate has been sensitized and is ready to be toggled with the primary input found earlier. All primary inputs that lead to the target gate have been defined at this point. This valuable information must be transferred from the working array to the array holding the primary input values.

The mechanized task of assigning these sensitizing logic values is complicated to program into code. Adding to the complexity is the fact that all of the gates can (and if fact, probably will) have a various number of inputs. This translates into a large amount of computer code overhead. In other words, much of the computer code will be spending valuable processor time checking and rechecking the gates to get their basic configurations. Couple this requirement with the endless combination or gate arrangements, and the task can seem quite daunting.

In this implementation, the strings are initially composed of the node inputs separated by an asterisk. The values assigned to each of these nodes can be inserted appropriately into the string. For example, a possible path from the target gate input, N4, to the primary input, “A”, would look like:

N4N3N2N1A

Adding the assigned nodes to the path would look something like:

N4-0N3-1N2-1N1-0A-1

The values given in the line above indicate that the target gate is some type of OR function (either OR or NOR) and the primary input A has its value set to 1. Obviously, modifying the string to contain these values takes some careful programming. It should be noted that it is not sufficient to just look at a partial string for identification without finding a limiting character, in this case a dash, - or an asterisk, *. Without the confirmation of a limiting character, it would be easy for the program to mistakenly find “N1” from the first two characters of the nodes “N11” or “N111”. To test the program code of this algorithm, a netlist was created with the similar names “A”, “AA”, “AAA”, and so on.

At this point in the Toggle algorithm, the array contains the values that sensitize the path to the target gate. Unfortunately, the job is only about one third of the way completed. It is necessary to look past the target gate and find the gates that fan out from the target. Unlike the gates on the toggle path which were set to allow signals to pass, the gates that are fed by the target gate should be desensitized so that they block the signal.

The steps up to this point have only applied to gates that are at least one level deep into the circuit. If the target gate was controlled exclusively by primary inputs, there was no need for a toggle path. However all gates need to be checked for fan out branches, regardless of the status of their inputs. The fan out gates that are fed by the target gate are desensitized using the same steps given above to sensitize the target gate. The only difference being in the logic level for the same gate function. For example, the AND functions now will be given a 0, and the OR functions will be given a 1. This prevents the gates from switching when the target gate toggles. Once these paths have been traced back to the primary inputs, the values that have been assigned are transferred back to the primary input array for safe keeping.

With these primary values now approaching the required vector pair, there is one more set of primary inputs necessary to complete the job. Once again the focus must be on the case where the target gate is not exclusively controlled by primary inputs. In other words, the target gate requires a sensitized toggle path. The circuit must be checked for gates that fan out from nodes along the toggle path. Since it is correctly assumed that all of the nodes along the toggle path will be switching, it is necessary to desensitize the gates that share these nodes. Again, the string is searched for the nodes in question. The difference is that in this search the nodes are compared to the entire netlist. When a fan out gate is located, all of the inputs to it (except the input on the toggle path) are set to the desensitizing level based on the function of the gate. Each input is then backtracked until all the primary inputs controlling that fan out gate are assigned a value.

At this point, assigning values to the primary inputs could cause a conflict with the assignment from an earlier stage of the algorithm. For example, a primary input assignment used to desensitize a gate fed by the target gate may not agree with the assignment required to desensitize a gate fanned out from the toggle path. In our program, this conflict is noted on the screen and allows the user to do a “reality check” if deemed necessary. Since one input is usually sufficient to lock the output of a gate, most logical circuit designs do not suffer from this conflict. The Toggle algorithm desensitizes a gate by assigning all of the remaining inputs to the locking value. The effect would be the same if only one of the inputs was set tot the locking value. This redundancy allows some tolerances with the inputs used to desensitize the gates.

2.3 Displaying and Interpreting the Results

The final result of this algorithm is simply a pair of vectors associated with each gate. For example, a gate may require 000100 and 000110 to cause it to toggle. This can also be displayed as 0001T0, where “T” denotes the primary input to be cycled. It is also possible to have “don’t care” values. Therefore 00x1T00 represents a valid pair of vectors that have an equal result toggling the target gate. Finally, the vector pair also may contain some flag settings if all of the inputs to the target gate are primary. In the code, the asterisk represents this flag. Thus, the vector pair may contain the following: 01****01, where the other variables have been set to desensitize the gates that are fanout branches from the target gate.

The Toggle algorithm can be an effective tool in circuit analysis. In most cases it is able to give the input vectors necessary to toggle a particular gate within the constraint that a minimum of incidental gates should switch. One of the most positive features of this algorithm is the fact that it targets a particular gate, and therefore does not have to waste processor time assessing an exhaustive list of input vectors. Another advantage to this algorithm is the fact that it is extremely flexible. It easily adapts to gates with any number of inputs.

Of course, the algorithm is not bulletproof. When implemented in code, the different test circuits could provide potential cases that would cause problems of various degrees. With an infinite number of circuit arrangements, it is virtually impossible to claim that the algorithm is 100% effective for all circuits. Invariably, reconvergent fanout causes the most problems. It also seems to cause the problems that require more complicated computer coding fixes. However, these wrinkles in the program were ironed out as they were encountered. The optimization process is an iterative one that balances performance time with algorithm results. As more test circuits with various topologies are encountered during testing, more steps will be required for the algorithm to handle the new situations. The development of this algorithm is an evolutionary process that continues to grow and improve.

2.4 Toggle Algorithm Examples

The following information provides several detailed examples of the Toggle algorithm using general test circuits as well as industry benchmark circuits. The algorithm was coded using Microsoft QuickBasic. Instead of using random names and numbers for the node designations, the names of friends, family, fictional characters, and other assoicates have been used. This lends a ceratain amount of interest to the test circuit, and also provides a forum to thank some of the people that were supportive and helpful in the creation of this project. The 40 logic gates are comprised of 160 names. For some of the simulations, the names were abbreviated to conserve computer memory resources. The full netlist for the circuit is given below:

AND, Cary, Adam, Agilent, Caton, Chuck

OR, Daneshvar, Drew, Dustie, Jayant, Jerri

AND, Doris, Kieu, Konrad, Phoenix, Pollock

OR, Frida, Rosa, Sai, Tranjan, Watauga

AND, Holmes, Sentra, Amanda, Benny, Cama

OR, Jackie, Constellation, Emerald, Heather, Jael

AND, Jamie, John, Lori, Maxwell, Paige

AND, Renee, Rahul, Savannah, Stanna, Toria

OR, Rokoske, Wes, Abba, Appalachian, Bjorn

OR, Jellineck, Kim, Piper, Sabrina, Val

AND, Binkley, Nissan, Agnetha, Annie, Artie

AND, Tektronix, Bruce, Camile, Cary, Daneshvar

OR, William, Doris, Frida, Holmes, Jackie

AND, Hoffman, Forest, ADE, Charlotte, Duke

OR, Houck, Janice, Justice, Jamie, Makki

OR, Jie, Molly, Orchard, Paraag, Phoebe

AND, Kakad, Renee, Rokoske, SigmaPiSigma, Stern

OR, LeCroy, Jellineck, Binkley, Blackman, Clarissa

OR, Mae, Dallas, Daniels, Edie, Fred

OR, Geoffrey, Tektronix, Posse, Tracy, William

AND, Jonathan, Geoffrey, Hoffman, Houck, Jie

OR, Michelle, Kakad, LeCroy, Mae, Morgan

AND, Karen, Beverly, Curt, Frank, Herb

OR, Robin, Reva, Sally, Michelle, -

AND, Spook, Sheila, Slap, Stephen, Steve

OR, Supper, Weldon, Will, Wu, Anna

AND, Yassoda, Mamola, Reinke, Jonathan, Keisha

OR, Alyse, Mecklenburg, Rebekah, Johnny, Lynne

AND, Boone, Sharer, Stephanie, Wexford, Bad

AND, Clements, Brandon, Dianne, Hazem, Inge

OR, Brice, Roger, Kevin, Marticia, Noblet

OR, IEEE, Staci, TauBetaPi, Wake, AWIS

AND, Issa, Gina, Howard, Darling, Blank

AND, Rodriguez, Mukherjee, Marta, Karen, Robin

OR, Taylor, Spook, Supper, Yassoda, Alyse

OR, Nick, Zhan, Kelly, Boone, Jim

AND, Onyx, Clements, Brice, Delinda, Ellery

OR, Prue, IEEE, Issa, Khanh, Pam

OR, Wendy, Rodriguez, Saurahb, Surya, Taylor

OR, Lisa, Nick, Onyx, Prue, Keith

Figure 7 shows the layout of the circuit. Since the test circuit is so large, it has to span two pages. The two nodes on the far right of Figure 7 (a) are continued onto Figure 7 (b). The two nodes on the far right of this figure are the outputs for the entire circuit. These figures show that the majority of the lines are primary inputs. The following examples will target gates that meet three different conditions:

1. All inputs are primary.

2. No inputs are primary.

3. Some (but not all) inputs are primary.

For the first condition, Gate 6 is chosen. Since all the inputs are accessable, a set of inputs to toggle the gate is trivial. In this case, the advantage of running the program is to provide the inputs which prevent the surrounding gates from switching unnecessarily. Running the Toggle program gives the expected results. Since the only device driven by Gate 6 is Gate 13, all of the inputs are geared toward desensitizing this one gate. To do this, the algorithm seeks to provide Gate 13 with one or more high logic levels. Therefore, the program gives 1’s for all of the inputs driving Gates 3, 4 and 5. This prevents Gate 13 from switching, regardless of the actions of the targeted gate.

Selecting Gate 13 for the target gate meets the requirements for the second condition. This gate is not driven by any of the primary inputs. Running the program gives the following results:

The Primary Toggle input: Kieu

The Toggle path: Kieu – Doris – Target Gate

The following 15 inputs are set high: Adam, Agilent, Bruce, Camile, Caton, Chuck, Drew, Dustie, Jayant, Jerri, Konrad, Phoenix, Pollock, Posse, and Tracy.

The follwing 12 inputs are set low: Amanda, Benny, Cama, Constellation, Emerald, Heather, Jael, Rosa, Sai, Sentra, Tranjan, and Watauga.

Figure 7 (a) One half of the large test circuit for the “Toggle” algorithm. The two nodes shown on the right are continued on the second half shown in Figure 7 (b).

Figure 7 (b) The second half of the large test circuit for the “Toggle” algorithm. The two nodes from the first half shown in Figure 7 (a) are used as inputs in this figure.

All other primary inputs are “don’t care” conditions as long as they are stable. Checking these results with the schematic, the algorithm provided acceptable results. The inputs that are set low sensitize the path to the targeted gate. The target path does toggle Gate 13. The gates set to high prevent adjacent gates from switching. This example provides a successful circuit analysis.

Selecting Gate 40 for the third condition is interesting because it not only has both primary and internal inputs, but also because it provides an observable output. Running the program gives the following results:

The Primary Toggle input which controls the target gate: Keith

The follwing inputs are set low: AWIS, Bad, Blank, Brandon, Darling, Delinda, Dianne, Ellery, Gina, Hazem, Howard, Inge, Jim, Kelly, Kevin, Khanh, Marticia, Noblet, Pam, Roger, Sharer, Staci, Stephanie, TauBetaPi, Wake, Wexford, and Zhan.

All other primary inputs are “don’t care” conditions as long as they are stable. None of the primary inputs is required to be set high. This is due to the fact that the target gate is an OR function. The low logic level will allow the gate to toggle. Obviously, any of the primary inputs to the gate can be used to toggle the output. In this case, the only choice is the primary input “Keith.” Once again, the Toggle program provided the correct test patterns necessary to target and toggle a logic gate within a given circuit.

With the goal of finding an efficient set of input vectors, further testing of the coded algorithm was conducted using ISCAS ’85 benchmark circuits. Figure 8 details the schematic for circuit “C17”. This is a small benchmark circuit comprised of 6 NAND gates. Although the circuit is not large, it does provide an interesting example that is easy to hand check. The results of the analysis are given in Table 3 with the following input order: 1 3 2 6 7. The digital values are represented with a 0’s and 1’s, while the toggled variable is once again represented with a T. The other inputs that do not come into play are represented with dashes to indicate a “don’t care” logic level.

Figure 8 The Schematic for Benchmark Circuit C17.

Table 3 The Vector Input Data for Circuit C17.

Gate	Vector Pair	Toggle
1	T 1 1 0 -	1
2	1 T 0 - 0	3
3	1 1 T 0 1	2
4	- 0 1 0 T	7
5	T 1 0 1 -	1
6	1 1 T 0 0	2

Since the benchmark circuit C17 provides an accepted structure, the circuit was modified to provide more data. Figure 9 shows the blank template used to provide more analysis. Replacing the blocks with other gates provided the data shown in Table 4. Although using multiple combinations of different gates in each of the test circuits is possible, all blocks were replaced with the same gates following the spirit of the original C17 circuit. The gates used to replace the NAND gates were the NOR, the AND, the OR, and the XOR.

Table 4 The Data for the Modified C17 Circuits.

Function	Gate	Vector Pair	Toggle
	1	T 1 0 1 -	1
	2	1 T 1 - 1	3
NOR	3	0 0 T 1 0	2
	4	- 1 0 1 T	7
	5	T 0 1 0 -	1
	6	0 0 T 0 1	2
	1	T 1 0 0 -	1
	2	0 T 0 1 0	3
AND	3	0 1 T 1 0	2
	4	- 0 0 0 T	7
	5	T 1 1 1 -	1
	6	0 1 T 1 1	2
	1	T 0 1 1 -	1
	2	0 T 1 - 1	3
OR	3	1 0 T 0 1	2
	4	- 0 1 0 T	7
	5	T 0 0 0 -	1
	6	1 0 T 0 0	2
	1	T - - - -	1
	2	- T - - -	3
XOR	3	- 1 T 0 -	2
	4	- 1 - 0 T	7
	5	T 0 1 1 -	1
	6	- 1 T 1 0	2

The next test circuit analyzed was the C432 benchmark. Incidentally, this is the same clustered circuit used to obtain laboratory measurements from an actual fabricated chip documented in Chapter 3 of this dissertation. This circuit is a medium-sized circuit of 70 gates. These gates include the following: INV, NAND, NOR, AND, and XOR. The 36 inputs are given to be: 1 4 11 17 24 30 37 43 50 56 63 69 76 82 89 95 102 108 8 14 21 27 34 40 47 53 60 66 73 79 86 92 99 105 112 and 115. A data summary showing every fifth gate obtained from this circuit is given in Table 5.

Figure 9 The Blank Template for the C17 Circuit. Each of the different blocks shown was replaced with different logic gates to provide the data shown in Table 4.

Table 5 The Data Summary for the C432 Benchmark Circuit.

Gate	Vector Pair	Toggle
5	1 0 1 0 T 0 1 0 1 0 1 0 1 0 1 0 1 0 - - - - - - - - - - - - - - - - - -	24
10	- - - - - - - - 1 T - - - - - - - - - - - - - - - - 1 1 - - - - - - - -	56
15	- - - - - - - - - - - - - - T 0 - - - - - - - - - - - - - - - - - - - -	89
20	- 1 - - - - - - - - - - - - - - - - T - - - - - - - - - - - - - - - - -	8
25	- - - - - - - - 0 T 0 1 - - - - - - - - - - - - - - - - - - - - - - - -	56
30	- - - 1 - - - - - - - - - - - - - - - - T - - - - - - - - - - - - - - -	21
35	- - - - - - - 1 - - - - - - - - - - - - - - - - - T - - - - - - - - - -	53
40	- - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - T - - - - -	86
45	- - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - - T	115
50	1 0 1 T 1 0 1 0 0 1 0 1 0 1 0 1 0 1 - - - - - - - - - - - - - - - - - -	17
55	0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 T - - - - - - - - - - - - - - - - - -	108
60	0 1 0 1 0 1 1 T 0 1 0 1 0 1 0 1 0 1 - - - - - - - - - - - - - - - - - -	43
65	0 1 T 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 - - - - - - - - - - - - - - - - - -	11
70	0 1 0 1 0 1 0 1 T 0 0 1 0 1 0 1 0 1 - - - - - - - - - - - - - - - - - -	50

The next benchmark circuit used was C880. This is a large circuit of 383 gates. The gates represented in the C880 circuit include: INV, NAND, NOR, AND, OR, XOR, and BUFFER. This circuit has 60 primary inputs given to be: 1 13 268 89 29 51 210 59 68 156 143 146 149 153 130 91 96 101 106 111 116 121 126 85 87 246 8 17 152 159 171 183 228 237 195 255 219 90 42 80 26 36 73 55 72 74 75 135 207 165 177 189 201 86 88 138 261 259 260 and 267. A data summary showing every tenth gate obtained from this circuit is given in Table 6.

Table 6 The Data Summary for the C432 Benchmark Circuit

Gate	Vector Pair	Toggle
10	0T------------------------00---------------0----------------	13
20	0T-------------------------0------------0--0----------------	13
30	----T---0-----------------------------0--0----0-------------	29
40	T-----0-0----------------01---------------------------------	1
50	T0----0-0----------------01--------------0------------------	1
60	T1--0-000----------------01----------0---100----------------	1
70	----0--0T-----------------------------0---------------------	68
80	00--T---------------------0--------------0-0--0-------------	29
90	00-----11-----------------0----------------0-T--------------	74
100	---0-0-------------------0-----------T0----0---------------	80
110	----0--0-------------------0----------T--0----0-------------	42
120	----0--0-------------------------------T-0----0-------------	80
130	----0--0-------------------0----------T--0----0-------------	42
140	-------T00-----------------1----------1--0----0-------------	59
150	-------T00-----------------1----------10-0----0-------------	59
160	-----------------------T------------------------------------	85
170	----0-0-----T1----------------------------------------------	91
180	----0-0-------T1--------------------------------------------	101
190	----0-0---------T1------------------------------------------	111
200	----0-0-----------T1----------------------------------------	121
210	0------1-----1----------T-----------------------------------	8
220	0----1-1-------1-------- T----------0-----------------------	17
230	-------T0----------------1----------1-0----0----------------	59
240	0----1-1-----------------T----------1---------------0-------	17
250	-1-001----1----------1-T--------1-1-1--0-----1--------------	159
260	-1-00--1----1--------1--T-------1-1-1---0----1--------------	171
270	-1-11--------1-----------T----1-1-----0---------------------	183
280	-1-1--1--------1----------T---1-1------0--------------------	195
290	--T-000-0-000000---0-1--0-1--------000--00------------------	210
300	-0T-01000-000-0000------1--0-1-0--0------00---0-------------	210
310	--1--1-1--------1----1-------T--1--1-------------00---------	255

(Table 6 is continued on the next page)

Table 6 (continued from previous page)

320	--1--1--1--------1---1--------T-1--1------------0-0---------	255
330	--1--1---1--------1--1--------T-1--1------------00----------	255
340	------------------------1------------T----------------1-----	90
350	----0--0-------------------0----------T--0----0-------------	42
360	----0--0-------------------0----------T--0----0-------------	42
370	-----------------------T-----------------------------1------	85
380	------------------------1------------T----------------1-----	90

CHAPTER 3: MAPPER COMPUTER AIDED DESIGN TOOL

As previously discussed, the fabrication of an electronic circuit is one of the most complicated and intricate tasks ever performed. The shrinking size of the technology and the growing complexity of the layouts cause the need for performance analysis to be considered early in the design process. Therefore many different CAD tools are necessary at all stages of the design. Ironically, a computer is necessary to create a computer [43].

Some CAD tools aid in the conversions between file types. These allow, for example, the creation of a circuit layout in Magic to be converted and logically checked using the digital analysis of IRSIM. The same layout can then create a Spice file for analog simulations [44].

Other software CAD packages work directly with the layouts to find any number of potential problems. Some tools can focus on the crosstalk induced through capacitance between the traces. Others find short circuits in the layout designs. These types of tool focus on circuit performance rather than the manufacturing problems. Still others try to analyze the physical layout to prevent manufacturing problems such as circuit layouts that tend to cause problems with masks used in fabrication [45] – [47].

The complexity of a software design package can vary. Some seemingly simple tasks require a great deal of computer effort. Other process steps require minimal computational power. Some tools focus directly on faults by using statistical methods

in conjunction with the effectiveness of a given set of test vectors [48]. Although the CAD tools used in the fabrication of CMOS circuits are diverse, they all share the goals of facilitating the design and fabrication process, as well as increasing the reliability of the finished product.

The goal of the Mapper CAD tool algorithm presented in this document is to analyze the gate level response of a circuit with defects inserted at the transistor level. The name “Mapper” has been given to the tool because it takes the effects of a defect implanted at the transistor level and transfers it, or “maps” it, onto a circuit at the gate level. To accomplish this, a library of defective gates must be fully defined and implemented in software. With this information, the software can analyze the gate level circuit, interpret the implanted transistor-level defect, and provide the complete switching profile of the digital circuit. In other words, it will compare the number of known (and unknown) gate switches in the defect-free circuit to the number of known (and unknown) gate switches in the defective circuit. This information is critical when testing a circuit using i_DDT test methods.

Because i_DDT testing is still a relatively new and growing field of study, the Mapper CAD algorithm is a unique tool. Other programs can provide the same information as the Toggle algorithm, even though they may use alternative methods for determining the required input data. However, the Mapper software is one of the first tools used to analyze a digital circuit in this manner to deliver valuable characteristic information for digital circuits. Both algorithms used together provide a powerful analysis method that greatly aids i_DDT testing.

The Mapper tool benefits from the results provided by the Toggle algorithm. An efficient set of test patterns is required to stimulate the circuit being tested. In fact, the netlists for both of the computer programs are very similar. Of course, the netlists are not interchangeable since the addition of the defective gates requires some slight modifications. The Toggle algorithm analyzes defect-free circuits; the Mapper CAD algorithm analyzes both defective and defect-free circuits. Both of the algorithms were developed and created for testing using the QuickBasic computer language. The rules of syntax and structure were followed to create functioning implementations of the algorithms [49], [50].

3.1 Mapper CAD Algorithm User Options

For the Mapper CAD algorithm to be useful, it should provide a menu for the user to navigate. This interaction allows the user to see the working circuit file, see the working input data file, or change these files as necessary. The user also has the choices of displaying a help file, running an analysis of the circuit, or exiting the program at any time. Figure 10 shows the high level overview of the Mapper CAD algorithm.

The first steps involve reading in the circuit data file. As this reading operation is being performed, the primary inputs are discovered and recorded for future reference. The option of reading in the input data file is not available until the circuit data file has already been entered. This restriction allows some error checking to be performed in the background without the user even being aware that it is taking place. Obviously, the file containing the list of primary inputs must match the list of primary inputs found in the circuit data file. This list can must match in name and number, but not in the same order.

Figure 10 The high level overview of the Mapper CAD program.

Another error checking procedure makes sure that none of the primary inputs is listed more than once. Yet another error check ensures that one of the primary inputs is given a “T” assignment. This special assignment means that this variable will be the one switched between 0 and 1 to stimulate the circuit during the analysis.

Other assignments allowed in the input data file are “A”, “V”, and “W”. Although these variables are generated by some of the defective gates in the circuit data file, they must be coded to be acceptable characters. This keeps the algorithm generic, allows a greater range of user control, and allows for larger circuits to be analyzed in smaller partitions if desired.

Because the shape of the letter A resembles an arrow pointing upwards, the “A” represents a logic level that would be pulled high in a defect-free circuit, but is undetermined because of a defect. Similarly, the “V” represents a logic level that would be pulled low normally, but is undetermined because of a defect. Various parts of the letter W resemble both upward and downward arrows, so the “W” represents a truly undetermined logic level with no indication of the level in a defect-free circuit. Depending on the defect type and defect location, a defective gate can produce a 0, a 1, or any of the three undetermined values as an output. Technically, the “A”, the “V”, and the “W” all represent an undetermined logic value, but are included since future iterations of the algorithm could find some benefit in making a distinction between the variables.

As in the previous coding used for the Toggle algorithm, the Mapper CAD computer code follows the same practices of modular programming. Smaller procedures are used instead of having one huge program list. This makes the code easier to write, read, document, and comprehend. Also, the same attention to double checking the information and error handling routines has been included in this implementation. Both program implementations provide a similar user interface, manipulate data in the same manner, and give a very consistent feel when using them in tandem.

3.2 Analysis of a Defective Circuit

Since the end goal of this algorithm is to compare a circuit containing transistor level defects with a defect-free circuit, the defective circuit must be analyzed first. Only then can the circuit be “fixed” and analyzed again for comparison. If a circuit does not contain a defect, then it is analyzed only to determine the number of gates that are switched with the given list of primary inputs. Of course, a comparison with another circuit can not be made. The software is very user friendly, and therefore it automatically determines whether a defective gate is present or not and reacts accordingly.

Figure 11 shows the basic decision process used to find the values of the gates. The workhorse in this algorithm is the “DoGate” procedure. It takes the gate function and the assigned input levels and uses this information to determine the output of the gate. This information is then distributed to the other nodes stored in the array. This process repeats until all of the gates are assigned a value of 0, 1, or one of the undetermined values.

Figure 11 The Defective Circuit Analysis Procedure.

Once all of the gates are given an output level of 0, 1, A, V, or W, the gate information is stored. With the important gate levels stored, this additional array information is removed from the array holding the gate and node names so it can be used again. In fact, when analyzing a defective circuit, this information must be used on four separate occasions. The array is used twice to analyze the defective circuit and twice again for the defect-free circuit.

To get the two input vectors that are used in each of the two runs, the “T” in the file list of primary inputs is replaced with a 0 and a 1 to create a pair of input vectors. For example, an input vector of:

100T001

becomes the vector pair:

1000001

and

1001001

because the “T” must be represented as a “0” in one case, and a “1” in the other case. This means that the process shown in Figure 11 must be repeated for the second input vector.

Each of the vectors in the vector pair provide a set of stored gate information. Once this information has been determined, the gate and node array is once again stripped of its excess logic assignments. The circuit can then be “repaired” to provide a comparison circuit. All the gates in the array are inspected individually. If a defective gate is found, it is replaced with a defect-free version of itself. At this point, the defective circuit has been transformed into a defect-free circuit.

3.3 Analysis of a Defect-free Circuit

If the circuit under test contains a defective circuit, the algorithm uses the process listed above before analyzing the defect-free version of the circuit. If no defective gate is included in the circuit under test, then the algorithm assumes that the information desired is simply the switching profile of the defect-free circuit. This is a valid assumption since the information obtained from a defect-free circuit can be useful in i_DDT research. In either case, this portion of the algorithm documented in this section is used for each and every circuit analysis, defective or defect-free.

The analysis of the defect-free circuit is essentially the same for the defective circuit. In fact, the same procedure, “TwoRuns”, is used for both versions of the circuit. The differences between the two runs are in the array holding the circuit gate and node information and in the variable numbers passed to the procedure when invoked. The “TwoRuns” procedure earned this name since every circuit requires two different analysis runs; one run is for the toggling variable “T” reset to 0, and the other run is for the case where “T” is set to 1.

Since this procedure is virtually identical to the previous case, the flow shown in Figure 11 is valid for the analysis of the defect-free circuit. Depending on the defect type and location, a defective circuit that is given an input vector comprised of only 0’s and 1’s can produce gate outputs that are undetermined: “A”, “V”, or “W”. On the other hand, the defect-free circuit given an input vector of all 0’s and 1’s will provide definite outputs of 0’s or 1’s. The defect-fee circuit can only provide undetermined logic values if it is given an input vector that contains undetermined variables. The engine driving these important Mapper CAD algorithm logic decisions is found in its library of gates.

3.4 The Library of Gates

Following the steps of the Mapper CAD algorithm, a point is reached where an output value must be assigned a 0, a 1, or an undetermined variable. To accurately make these decisions, a complete list of the gates must be consulted. In this case “complete” means that both defective and defect-free gates are listed and given equal treatment. The library provides the logical gate level operation of all of the gates, both defective at the transistor level as well as the defect-free versions. Also as important, this library must be able to handle all the various input combinations that can be presented to the gates. The library of gates which has been defined for the Mapper CAD code is documented in Appendix A. The listing of the actual QuickBasic software code used to check this algorithm is given in Appendix B.

To show how a gate is entered into the library, a simple inverter is considered. Figure 12 shows the defect free inverter circuit. Table 7 shows the truth table giving the expected output of the inverter under all input conditions. The defect-free inverter provides the inverted input level on the output. Of course, an undetermined input results in an undetermined output.

Figure 12 The Defect-free Inverter Circuit. This gate inverts the logic level of the input. If the input is undetermined, then the output is undetermined.

Table 7 The Truth Table for the Defect-free Inverter Circuit.

A	Z
0	1
1	0
W	W

The logic algorithm that would be used to represent the defect-free inverter in computer code of any computer language would follow the pseudo-code given below:

If the INPUT is ZERO, then the OUTPUT is ONE.

If the INPUT is ONE, then the OUTPUT is ZERO.

If the INPUT is UNDETERMINED, then the OUTPUT is UNDETERMINED.

For comparison, the defective inverter is considered. Figure 13 shows the defective inverter schematic. An open circuit prevents the nmos transistor from pulling the output to a low logic level. However, if the input to the inverter is low, then the gate will appear to be fully functional. This transistor level defect shows its logic level implications in the truth table given in Table 8.

Figure 13 The Defective Inverter Circuit.

Table 8 The Truth Table for the Defective Inverter Circuit.

A	Z
0	1
1	V
W	W

The logic algorithm that would be used to represent this defective inverter in computer code of any computer language would follow this pseudo-code:

If the INPUT is ZERO, then the OUTPUT is ONE.

If the INPUT is ONE, then the OUTPUT is UNDETERMINED (ZERO).

If the INPUT is UNDETERMINED, then the OUTPUT is UNDETERMINED.

The example above gives a great deal of information. A gate with a defect is represented at the transistor level. The effects of this transistor level defect are shown at the logic gate level (under certain input conditions) as represented in the truth table. Finally, the algorithm for some generic computer code is given to represent this logic gate with a transistor level defect.

For this simple circuit example, the output is easy to follow. As the complexity of the gates increases, so does the impact of the defects and the undetermined variables. This library of gates must be able to handle all input combinations of 0’s, 1’s, and undetermined variables. Therefore the inputs to these digital circuits can no longer be considered binary.

In a binary system, a logic gate with n inputs can be exhaustively characterized using a truth table with 2ⁿ rows. Thus, a 4-input AND gate can have all input combinations described with a truth table of 16 rows, numbered from 0000 to 1111. Simply adding one possible level other than a 0 or a 1 to the input gives a truth table of 3ⁿ rows. In this case, a truth table for the same 4-input AND gate would have 81 rows. Fortunately, some reduction is possible in many cases. For example, if one or more of the inputs to a defect-free AND gate is 0, then the output will be a 0. Some “don’t care” values can drastically reduce the truth table.

As mentioned before, the defective circuit creates undetermined values. Even though the defect-free circuit can not create an undetermined value, it must be able to handle them. Since the defect-free circuit can be given undetermined values, the library must be able to provide results for single as well as multiple undetermined variables. This method of programming the tool to be generic increases the usefulness of the algorithm.

3.5 Displaying and Interpreting the Results

Using the complete library of gates, the algorithm constructs 2 or 4 strings of variables. The characters represented are the 0, the 1, the A, the V, and the W. These variables represent an ordered list of the gate level logic outputs. If the netlist of the circuit under test does not include a defective gate, then only 2 strings of variables are created. Each of these two strings represents the circuit response obtained from one half of the input vector pair constructed by switching the “T” toggle variable from 0 to 1. If the netlist does include a defective gate, then 4 strings are available. These represent the pair of responses from the defective circuit and the pair of responses from the defect-free circuit.

To create the comparison between the strings, the Mapper algorithm employs a small procedure to compare the variable strings bit-by-bit and count the number of switching gates. A gate switching from a definite 0 to a definite 1, or vice versa, counts as a gate switch. A gate that remains undetermined, or possibly switching between undetermined values such as a “V” to a “W”, is counted as an undetermined gate switch.

The computer code used to prove the Mapper algorithm in this case makes a call to the “CountUp” procedure to get the number of switching gates. The screen displays the variable strings used to store the gate information. The number of switching gates is provided. The number of undetermined switches is given below. If a defective gate is included, then this same information is given for the defective circuit as well as the defect-free circuit the computer program automatically generated from the original netlist. The end result of the Mapper CAD tool software is the switching profile of a defective circuit compared with the defect-free version of the same circuit. Examples of this algorithm are given below.

3.6 Mapper CAD Algorithm Examples

The computer code implementation of the Mapper CAD algorithm has successfully analyzed many circuits. The CAD tool is supposed to facilitate circuit analysis. Therefore using the tool makes the computer analysis is a simple job. Verifying the data by hand is now the time consuming task. For the examples given below, simple circuits are used to verify the code and to confirm accurate results. To show examples of the code functioning under different conditions, the following simulations are performed and analyzed:

1. A Defect-free circuit with absolute test vectors.

2. A Defect-free circuit with undetermined test vectors.

3. An Open-defect circuit with absolute test vectors.

4. An Open-defect circuit with undetermined test vectors.

The first case is represented in Figure 14. All of the gates in this circuit are defect-free. The “T” in this example represents a toggle from 0-to-1 or from 1-to-0. This primary input is the one used to control the test switching of the circuit. The other primary inputs are set to sensitize the circuit to allow as many of the gates as possible to switch. In this case, the toggle flows all the way to the one observable output of the circuit. In the spirit of fully testing the code, the input vectors were given in the random order of B=0, C=T, E=0, A=0, F=0, and D=1.

Figure 14 The Defect-free Circuit “GATES11.TXT” Using Absolute Test Vectors Found in “INPUT11.TXT”. In this case, the word “absolute” refers to the fact that all inputs are either a 0 or a 1. The letter “T” is acceptable since it represents the absolute and determined values of both 0 and 1.

Running the computer code using the given input file gives the following results:

=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=

Defect free circuit gate information: 1010101

1001011

Total switches in the defect-free circuit: 4

Undetermined switches in the defect-free circuit: 0

=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=

Figure 15 shows the same circuit under different conditions. In this case, the input vector does not contain solely absolute digital values. An undetermined value of A, V, or W can provide a strikingly different result. The test vector is once again given in the random order of B=1, C=T, E=0, A=W, F=0, and D=1. This vector differs from the above example by setting the primary input A to a W. Also, for this undetermined variable to affect the circuit, the primary input B must be set to 1 to allow the effects of the variable to pass through this NAND gate.

Figure 15 The Defect-free Circuit “GATES11.TXT” Using the Undetermined Test Vectors Found in “INPUT11A.TXT”. In this case, the W is assigned to one of the primary inputs.

Running the computer code using the given input file gives the following results:

=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=

Defect free circuit gate information: WW10WW1

WW01 0 1 1

Total switches in the defect-free circuit: 2

Undetermined switches in the defect-free circuit: 4

=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=

Simply changing one of the primary inputs to an undetermined value drastically affects the results of this circuit. The information shows that one gate changes from a 1 to a 0, while another changes from a 0 to a 1. This gives the two switches in the defect-free circuit. However, four of these gates are switched from an undetermined state to either a 0, a 1, or another undetermined state. Since these states are by definition undetermined, they can not be counted as full switches. The gates may be switching, but there is no way to know for sure. The information given shows that this circuit and test vector pair cause at least 2 gates and at most 6 gates to switch.

Figure 16 The Defective Circuit “GATES19.TXT”. This circuit contains one defective NAND gate, as shown. The other primary inputs from the “INPUT19.TXT” file are set to prevent the undetermined values from reaching the observable output J. Changing either E or F to a 0 would allow the undetermined values to pass through the NOR gate.

The defective NAND gate shown in Figure 16 assigns undetermined values to the nodes past the defective gate output.. The input vector is given to be A=1, B=T, E=1, and F=1. Running the computer code with this given information provides the following:

=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=

Defective circuit gate information: WW0101

WW0101

Defect free circuit gate information: 100101

010101

=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=

Total number of switches in the defective circuit: 0

Undetermined switches in the defective circuit: 2

Total switches in the defect-free circuit: 2

Undetermined switches in the defect-free circuit: 0

=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=

This information shows that the defective circuit provides zero definite switches and two undetermined gates. The defect-free circuit would provide two definite switches and zero undetermined gates.

Figure 17 The Defective Circuit “GATES19.TXT”. The input information found in the file “INPUT19A.TXT” gives an undetermined value for F as well as the sensitizing value of 1 for E. Therefore all of the gate outputs in this example are undetermined.

Figure 17 shows the defective circuit and the input vector of A=1, B=T, E=1, and F=V. Running the computer code with this given information provides the following:

=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=

Defective circuit gate information: WWWWWW

WWWWWW

Defect free circuit gate information: 10WWWW

01WW 0 1

=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=

Total number of switches in the defective circuit: 0

Undetermined switches in the defective circuit: 6

Total switches in the defect-free circuit: 2

Undetermined switches in the defect-free circuit: 4

=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=

As expected, Figure 17 and the computer simulations confirm that all of the gates are undetermined. Even with the defective gate replaced, some undetermined values are still present due to the “V” assigned to one of the primary inputs. This example, the previous experiments, and many other test circuits not shown in this document have shown that the Mapper CAD tool provides correct and useful results.

3.1 Mapper CAD Algorithm User Options

Figure 10 The high level overview of the Mapper CAD program.

3.2 Analysis of a Defective Circuit

Figure 11 The Defective Circuit Analysis Procedure.

100T001

becomes the vector pair:

1000001

and

1001001

because the “T” must be represented as a “0” in one case, and a “1” in the other case. This means that the process shown in Figure 11 must be repeated for the second input vector.

3.3 Analysis of a Defect-free Circuit

3.4 The Library of Gates

Figure 12 The Defect-free Inverter Circuit. This gate inverts the logic level of the input. If the input is undetermined, then the output is undetermined.

Table 7 The Truth Table for the Defect-free Inverter Circuit.

A	Z
0	1
1	0
W	W

The logic algorithm that would be used to represent the defect-free inverter in computer code of any computer language would follow the pseudo-code given below:

If the INPUT is ZERO, then the OUTPUT is ONE.

If the INPUT is ONE, then the OUTPUT is ZERO.

If the INPUT is UNDETERMINED, then the OUTPUT is UNDETERMINED.

Figure 13 The Defective Inverter Circuit.

Table 8 The Truth Table for the Defective Inverter Circuit.

A	Z
0	1
1	V
W	W

The logic algorithm that would be used to represent this defective inverter in computer code of any computer language would follow this pseudo-code:

If the INPUT is ZERO, then the OUTPUT is ONE.

If the INPUT is ONE, then the OUTPUT is UNDETERMINED (ZERO).

If the INPUT is UNDETERMINED, then the OUTPUT is UNDETERMINED.

3.5 Displaying and Interpreting the Results

3.6 Mapper CAD Algorithm Examples

5. A Defect-free circuit with absolute test vectors.

6. A Defect-free circuit with undetermined test vectors.

7. An Open-defect circuit with absolute test vectors.

8. An Open-defect circuit with undetermined test vectors.

Running the computer code using the given input file gives the following results:

=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=

Defect free circuit gate information: 1010101

1001011

Total switches in the defect-free circuit: 4

Undetermined switches in the defect-free circuit: 0

=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=

Figure 15 The Defect-free Circuit “GATES11.TXT” Using the Undetermined Test Vectors Found in “INPUT11A.TXT”. In this case, the W is assigned to one of the primary inputs.

Running the computer code using the given input file gives the following results:

=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=

Defect free circuit gate information: WW10WW1

WW01 0 1 1

Total switches in the defect-free circuit: 2

Undetermined switches in the defect-free circuit: 4

=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=

Defective circuit gate information: WW0101

WW0101

Defect free circuit gate information: 100101

010101

=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=

Total number of switches in the defective circuit: 0

Undetermined switches in the defective circuit: 2

Total switches in the defect-free circuit: 2

Undetermined switches in the defect-free circuit: 0

=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=

This information shows that the defective circuit provides zero definite switches and two undetermined gates. The defect-free circuit would provide two definite switches and zero undetermined gates.

Figure 17 shows the defective circuit and the input vector of A=1, B=T, E=1, and F=V. Running the computer code with this given information provides the following:

=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=

Defective circuit gate information: WWWWWW

WWWWWW

Defect free circuit gate information: 10WWWW

01WW 0 1

=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=

Total number of switches in the defective circuit: 0

Undetermined switches in the defective circuit: 6

Total switches in the defect-free circuit: 2

Undetermined switches in the defect-free circuit: 4

=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=

CHAPTER 4: DATA MEASUREMENTS

Although the need for additional electronics testing strategies is virtually unquestioned, the application of new test methods such as i_DDT has been slow to develop. Because the dynamic power supply current is such a difficult parameter to measure, the practical applications of this testing method are scrutinized. Additionally, simply measuring the results is only half of the story. The measured results must be interpreted properly in order to create a viable weapon in the battle of fault detection.

Another obstacle in hindering the development of i_DDT testing is the intricate process required to obtain a circuit with controlled defects. Finding a defect-free integrated circuit (IC) off the shelf is simple and inexpensive. However, a hit-and-miss approach to finding an IC with a known defect is challenging, bordering on impossible. To solve this problem, test circuits must be designed with implanted defects, and then sent to a manufacturer to be fabricated. This process costs not only time, but money as well. The advantage of this process is the high level of control over the defective circuit, not to mention the level of control over the defect-free circuit used for comparison.

Due to the facts mentioned above, it is not surprising that true measured data in technical publications is difficult to find. Data obtained through computer simulations is much more common. Not only are the processes of physical collection and data interpretation extremely challenging, the corresponding simulation results are available in a fraction of the time using computer resources that are readily available. Computer

simulations also do not suffer the distorting affects of noise and losses seen in the true laboratory setting. However, this lack of distortion does lead to correlation problems. The goal of the measurements presented in this chapter is to provide various examples of circuits, their ideal simulations, and the corresponding careful measurements.

4.1 Measurement Challenges

One of the first issues addressed when planning an i_DDT measurement is the issue of “on-chip” or “off-chip” measurements. This aspect is important since an on-chip measurement basically requires additional circuitry added to the original design. The output of this additional circuitry could be a simple digital signal giving a “pass/fail” response [52].

The measurements presented here are measured off-chip. This provides some flexibility in the types of circuits that can be measured with this method. Figure 22 shows the circuit used to analyze the circuits. A 1k-ohm resistor on the power line provides a small voltage drop under DC conditions. This drop is not large enough to affect the circuit in any appreciable manner, but does allow an inspection of the i_DDT current using Ohm’s Law.

Another interesting point that becomes apparent with the help of Figure 22 is the fact that more than one circuit can be measured at the same time. In most of the test circuits shown in these examples each of the devices has dedicated power and ground lines. In addition, the same buffered inputs are used to stimulate all of the circuits. Therefore, a defect-free circuit can be measured side-by-side with a defective circuit. This allows comparisons that make delay faults very visible since the measurements are lined up with respect to time. Measuring defective circuits in this side-by-side manner

Figure 22 The general method used to make the i_DDT measurements.

can also provide interesting data. Of course this method could be used to measure circuits on different chips, but having multiple circuits on a single chip is not only convenient but also levels out the effects of process variations.

Among the many hurdles to overcome when making measurements is the fact that the wires and traces themselves can distort signals. Each wire has its own set of transmission properties. Any structure can radiate and absorb waves. This loss of certain frequencies greatly affects the measured signal seen on these lines. For example, a sharp pulse sent down a length of wire can lose the higher frequency components. The end result is a pulse that is skewed in time and distorted in magnitude and duration. Unfortunately, these sharp pulses containing higher frequency components are the signals expected from i_DDT currents [53], [54].

Another challenge facing the i_DDT testing method is the fact that the shrinking technology allows larger background leakage currents. These larger currents impact all current testing methods, not just i_DDT [55], [56]. Because i_DDT depends greatly on the process used in fabrication, the results must be repeated each time the technology size is reduced. Once again, the testing is attempting to keep up with the cutting edge of technology. The test circuits in the examples presented in this work represent the 0.5mm process using the 3-metal technology file SCN3ME_SUBM. The Spice computer simulations were created with 40-pin DIP package information and transistor data provided by the manufacturer, The MOSIS Service [57].

Another omnipresent issue in the realm of electronic data measurements is the quality of the ground. Ground loops and ground currents can cause fluctuating potentials on what is considered to be zero voltage potential. Digital switching of inputs and outputs can create ground bounce. The lengths of the power and ground connections between the power supply and the test circuit should be minimized. Also, the minimal length of the ground connection at the end of the measuring probe is critical in the reduction of ringing noise [58] – [60]. Fortunately, many of these grounding concerns can be addressed by the types of equipment used to make the laboratory measurements.

4.2 Laboratory Equipment

The quality of the measured data is directly proportional with the equipment used in the experiments. Figure 23 shows an early attempt to measure i_DDT currents on a pair of adder circuits. The trace shown in Figure 23 (a) gives a larger pulse in magnitude, but similar in duration. Figure 23 (b) shows the defective circuit under the same conditions giving visibly different results. This data was collected with the Tektronix TLA 720

Figure 23 (a) and (b) Definite differences between defect-free and defective adder circuits. The good circuit on the left provides a large pulse. The open in the defective adder leads to a smaller i_DDT pulse.

Logic Analyzer system. The test patterns were generated with the 64-channel TLA 7PG2 module and the P6470 TTL/CMOS probe. The digital signals were measured with the TLA 7N2 module. Finally, the analog signals were measured with the dual oscilloscope TLA 7D1 module and a 1-GHz P6243 probe. Similar measurements can be made with the optional 3.5-GHz P6330 differential probe.

To improve the measurements, several steps were necessary. The first attempt to increase the resolution was a substantial investment in superior measurement equipment. From this point on, all of the measurements provided have been created with the Tektronix TDS 6604 Digital Storage Oscilloscope and the 6-GHz P7260 probes. With the additional bandwidth of the probes in unison with the ability of the machine to measure up to 20 gigasamples per second, the resolution of the traces became much more detailed. In fact, the smooth pulse displayed as an average by an older oscilloscope is revealed to be a combination of oscillations with newer equipment.

Ironically, the addition of superior equipment increased effects of noise. The higher bandwidth of the probes showed the unwanted ringing that could not be seen on other oscilloscopes. Therefore, the accepted measurement practices mentioned above were carefully followed. Also a new piece of equipment was designed and fabricated.

Figure 24 shows the two-layer “Generic Test Board.” The name of the board reflects the fact that the board was designed to facilitate the testing of a wide variety of chips. Ideally the board holds a 40-pin DIP package which is commonly provided by the

Figure 24 The layout of the Generic Test Board. The location of pin 1 is marked with a “1.” Because the text in the center of the figure is located on the back side, it reads “UNC-Charlotte” shown in reverse. The text on the bottom line reads “Generic Test Board Rev. 2 S. Thomas K. Miehle 2002.”

chip manufacturer. However, smaller chips can be accommodated assuming that the pin spacing remains uniform. The traces on the board are made as short as possible to lower the unwanted resistance and inductance. A small “prototype” area was incorporated to allow for any additional components that may be required. Most importantly, the unused space is filled with a ground plane. The idea is to shield the lines from induced high frequency noise. This piece of measurement equipment was designed using the software and the recommendations provided by the manufacturer, PCB Express [61].

The use of the Generic Test Board helped to provide better measurements. Also, the connections between the board and the power supply, including the lengths of the V_DD line resistor leads, were kept to a minimum. Even though the Agilent E3631A power supply is well regulated, a 0.1mF capacitor was used on the board. Most notably, the ground connections on the tips of the oscilloscope probes were kept to an absolute minimum. Although some measurements required a length of wire between the tip and the ground, most instances used a short wire soldered onto the ground plane of the Generic Test Board. This significantly reduced the ringing seen in the measured data. Although the use of this test board required the investment of extra time and effort, the results showed vast improvements over typical plastic breadboard measurements. Superior equipment, wise choices, and careful measurement practices produce exceptional and repeatable results.

4.3 Measured Data Summary

Using the equipment and the practices outlined above, the following data was collected from several defect-free and defective circuits. The defects in a circuit can be categorized as “opens” and “shorts.” An open is the lack of a designed connection, and a short is the presence of an unwanted connection. Depending on the nature of these defects and their location in the circuit, they can cause innumerable problems. The logic levels can be incorrect, the paramaters can be faulty (such as leakage currents flowing into the substrate), as well as transient problems that cause temporary delays and noise.

The data is summarized in Figures 25 through 69. Each figure has been divided into four sections, (a) through (d). Typically, section (a) shows a gate level or transistor level schematic of the circuit, as well as the pin names and pin numbers. The inputs used to stimulate the circuit are also presented. The caption provides some additional information, such as the circuit name and the chip number.

Section (b) typically shows the transistor layout of the complete circuit. The layouts follow the design rules of the Magic software package [62], [63]. In cases where showing the layout of the circuit would be repetitive, some other photograph or related piece of information is presented. This other information could include a portion of the circuit, or some other related electronics.

Sections (c) and (d) show the i_DDT information. Section (c) graphically provides the Spice simulations [64]. The file generated from the layout was modified to include not only the circuit and the padframe, but also the package and the measuring equipment. A sample of this additional code is give in Appendix C. The captions of section (c) provide the magnitude and duration of each i_DDT pulse. For comparison, section (d) shows the measured results. Again, the caption provides the numeric information. With a great deal of visual and text information, the following figures attempt to fully characterize and document the i_DDT responses for many basic electronic circuits.

Figure 25(a) Logic schematic for the defect free inverter circuit “good_inv1” on chip T26B-CJ. As shown, the input A is routed through a buffer before reaching the inverter circuit. The test input is switched from low to high and back to low.

Figure 25(c) Simulated waveforms for the inverter circuit “good_inv1”. The first transition gives an i_DDT pulse lasting approximately 10ns with a maximum of 50mA and a minimum of -24mA. The second transition gives a pulse that is impressive in both its magnitude as well as its duration. The -225mA pulse lasts nearly 25ns.

Figure 25(b) The “good_inv1” inverter circuit layout in Magic detailing the connected padframe portion of the chip. The buffer circuitry shown in the lower left hand part of the figure smaller than the padframe above it, yet larger than the inverter shown near the middle of the figure.

Figure 25(d) The measured data for the defect-free inverter circuit “good_inv1”. The first switch gives an i_DDT pulse of magnitude 430mA lasting 9.2ns. The second i_DDT pulse is -480mA in size and 8.8ns in duration.

Figure 26(a) Logic schematic for the defective inverter circuit “def_inv2” on chip T26B-CJ. This defect is a 1l open in the power supply line. The transistor sizes for this set of inverter test circuits are 2l x 10l for the pmos and 2l x 5l for the nmos.

Figure 26(c) Simulated data for the defective inverter circuit “def_inv2”. The larger initial i_DDT pulse (77mA for 8ns) is a result of the initial state assumed by the simulation software. The additional i_DDT pulses (38mA for 5ns) are a result of the inverter never being able to draw a current from the broken power line.

Figure 26(b) The Magic software layout of the defective inverter circuit “def_inv2”. The figure shows the break in the power supply line.

Figure 26(d) The measured data for the defective inverter “def_inv2”. The first i_DDT pulse lasts 13.2ns with a range of –225 to 345mA. The second pulse lasts 8.4ns and gives a range of –340 to 190mA. These pulses should be compared with the third and fourth simulated pulses.

Figure 27(a) Logic schematic for the defective inverter circuit “def_inv3” on chip T26B-CJ. This defect is a 3l open in the Ground line. Again, the transistor sizes for this set of test circuits are 2x10l for pmos and 2x5l for nmos.

Figure 27(c) The simulated data for “def_inv3”. The first transition causes a 43mA i_DDT pulse for nearly 11ns. The second causes a 40mA pulse for 7ns. This current must be leaked or shared between the other devices. In fact, it would be reasonable to assume the area under the positive half of the curve is equal to the area under the negative half. In other words, the net current flowing through the device would be zero for the ideal simulations only.

Figure 27(b) The layout for the defective inverter circuit “def_inv3”. The 3l open in the ground line is clearly seen in the lower right corner of the figure.

Figure 27(d) The measured data for the “def_inv3” defective inverter circuit. The first transition gives a 350mA i_DDT pulse lasting 9.2ns. Of course, this does not include the ringing clearly shown in this measurement. It is comforting to note that the simulation appears to show some ringing as well. The second pulse shown in the measured data gives a -420mA pulse lasting approximately 8.4ns.

Figure 28(a) The logic schematic for the defective inverter circuit “def_inv4” on chip T26B-CJ. This defect is a missing via between poly and metal 1 on the gates of the transistors. Again, the sizes for these circuits are 2x10l for pmos and 2x5l for nmos.

Figure 28(c) This is the simulated data for the defective inverter circuit “def_inv4”. This is an interesting case because the gates of both transistors are floating at the same voltage. The first pulse is an 8ns i_DDT disturbance of 45mA. The second is a nearly identical pulse of 47mA lasting for 8ns.

Figure 28(b) The Magic layout for the defective inveter circuit. As mentioned previously, the transistors are sized differently and can be clearly seen in the figure. The missing via is located on the bottom part of the middle trace.

Figure 28(d) The measured data for “def_inv4”. The first i_DDT pulse of 410mA lasts for 6.9ns. The second pulse of negative 390mA lasts for 6.8ns. As in the previous measured example, some ringing is clearly shown.

Figure 29(a) The logic schematic for the defective inverter circuit “def_inv5” on chip T26B-CJ. In this case, the defect is an open on the gate of the pmos. Therefore the transistor used to pull the output high will be unpredictable.

Figure 29(c) The simulated data for the “def_inv5” inverter circuit. With the upper transistor floating at an obviously low voltage, the upper transistor is on. Therefore when the lower transistor is decidedly switched on, a relatively large i_DDQ of 1mA flows unimpeded from the power supply to ground. This current is orders of magnitude larger than the expected i_DDT pulses.

Figure 29(b) The Magic software layout for the defective inverter circuit with a floating pmos gate. The nmos section of the circuit is intact and should function normally.

Figure 29(d) The measured data gives results similar to the previous measurements. The first transition causes a 6.8ns i_DDT pulse ranging from negative 340 to 430mA. The second switch causes a 7.6ns pulse between negative 540 and 220mA. The floating gate obviously does not allow the defective transistor to turn on and allow the large I_DDQ seen in the simulations.

Figure 30(a) The logic schematic for the defective inverter circuit “def_inv6” on chip T26B-CJ. This defect is an open on the gate of the nmos transistor. Similar to the previous example, one of the transistors is intact and should function properly.

Figure 30(c) The simulated data for the “def_inv6” circuit. Both i_DDT pulses are 6ns wide. The first is 41mA, and the second is 38mA. It is interesting to note that the similar defect in the previous example caused a very different outcome. The nmos transistor is obviously OFF (or at least closer to OFF than ON). The conclusion is that the simulator assumes unconnected nodes float low.

Figure 30(b) The Magic layout for the defective inveter “def_inv6” shown upside-down. The implanted defect is similar to the previous example, however the nmos gate is floating instead of the pmos. The output should never be able to be pulled low unless the floating gate floats high, thus turning on the transistor. In any event, the user will have no control over the output.

Figure 30(d) The measured data for the “def_inv6” inverter circuit. The first transition causes a 6.8ns i_DDT pulse ranging between negative 350 and positive 450mA. The second i_DDT pulse lasts 6.4ns and gives a magnitude range between negative 430 and positive 290mA.

Figure 31(a) The schematic for the defect-free nand circuit “good_nand1” on chip T26B-BV. The transistors have been sized 2l by 10l for the pmos and 2l by 5l for the nmos.

Figure 31(c) The simulated data for the “good_nand1” circuit. The 8 transitions give the following i_DDT results:

35mA for 2ns, 38mA for 4.6ns, 90mA for 9.2ns, -270mA with a 30ns recovery, 26mA for 2ns, 41mA for 6.2ns, 86mA for 9.2ns, and -270mA with a 30ns recovery.

Figure 31(b) The Magic layout of the “good_nand1” circuit. The large section on the right side of the figure is the padframe. The traces on the left side route the padframe ports to the buffers and the nand gate output.

Figure 31(d) The measured data for the “good_nand1” circuit. The results are:

-225mA for 8.8ns, 180mA for 12.8ns, 205mA for 11.2ns with a DC offset of 185mA, -170mA for 8.4ns, -205mA for 6.4ns, 185mA for 8.8ns, 210mA for 9.6ns with a DC offset of 185mA, and

-175mA for 8.8ns.

Figure 32(a) The schematic for the defective nand circuit “def_nand2” on chip T26B-BV. The open in the power supply line should prevent nearly all i_DDT power flow into the circuit.

Figure 32(c) The simulated data for “def_nand2”. When Input A switches while Input B is high, an i_DDT pulse of 108mA lasting for 7ns is seen. When all of the other switches occur, the result is a 45mA pulse lasting for a mere 2ns. This result indicates virtually no response, and is the expected result considering the severity of the defect.

Figure 32(b) The Magic layout for the defective nand circuit “def_nand2”. The open defect in the power supply line can be seen clearly in the upper left hand portion of the figure.

Figure 32(d) The measured data for the “def_nand2” circuit. The general trend of the i_DDT pulses agrees with the simulation. However, the magnitudes are as follows:

175mA for 10.4ns, 181mA for 7.2ns, 181mA for 9.6ns, -150mA for 9.6ns,

-162mA for 7.2ns, 196mA for 7.6ns, 180mA for 8ns, and –118mA for 8.8ns.

Figure 33(a) The schematic for the defective nand circuit “def_nand3” on chip T26B-BV. As in the previous circuit, the dramatic open in the ground of the power supply line should lead to a significant change in i_DDT signatures.

Figure 33(c) The simulated data for the “def_nand3” circuit. The 8 transitions give pulses that are all very similar. Each is approximately 54mA in magnitude and approximately 5ns in duration.

Figure 33(b) The Magic layout for the “def_nand3” circuit. The open defect in the ground line can be seen clearly in the bottom left hand part of the figure. This defect explains the noticeable reduction in the i_DDT pulses seen in both the simulations and measurements.

Figure 33(d) The measured results of the “def_nand3” circuit. The results are:

-171mA for 10.4ns, 130mA for 7.2ns, 161mA for 9.6ns, a 340mA pulse with an 80ns recovery time, -113mA for 8.8ns, 179mA for 8.8ns, 117mA for 10.4ns, and finally another large pulse of 351mA with a very large recovery time of 88ns.

Figure 34(a) The schematic for the defective nand circuit “def_nand4” on chip T26B-BV. The missing via (essentially an open defect) is located on both gates of transistor number 1.

Figure 34(c) The simulation result for the open defect are the same as those seen in the previous example with no connection on the ground line. The i_DDT pulses are 54mA lasting approximately 5ns. This result is no surprise. The connected floating gates prevent the transistors from being on at the same time. Therefore in simulations, the result is equivalent to an open in the line.

Figure 34(b) The Magic layout of the defective nand circuit “def_nand4”. Although difficult to detect in the figure, the missing via is located on the middle trace on the left hand side of the figure.

Figure 34(d) The measured data for “def_nand4”. With the exception of a great deal of ringing, as well as the addition of some slight DC offsets, the i_DDT pulses are very consistent.

-190mA for 10.4ns, 181mA for 11.2ns, 184mA for 10.4ns, -196mA for 9.6ns,

-215mA for 11.2ns, 196mA for 10.4ns, 193mA for 11.2ns, and finally -206mA for 10.2ns.

Figure 35(a) The schematic for the defective nand gate “def_nand5” on chip T26B-BV. This defect is similar to the previous example, and therefore is expected to produce similar results. The only difference in this case is the transistors on the second input line are the ones targeted by the implanted defect.

Figure 35(c) The simulated data for “def_nand5”. For the reasons explained in the previous example, all of the i_DDT pulses are essentially identical. In this case, they are all approximately 40mA lasting about 5ns each.

Figure 35(b) The layout in Magic software for the defective nand gate “def_nand5” on chip T26B-BV. The defect can be seen clearly on the trace at the bottom section of the figure. The open connected to the gates prevents the input from controlling either one of the transistors.

Figure 35(d) The measurements of the “def_nand5” circuit. With the exception of some ringing and slight DC offset, the results are as expected. The i_DDT pulses are as follows:

-187mA for 8ns, 171mA for 11.2ns, 190mA for 9.6ns, -253mA for 8.8ns,

-190mA for11.4ns, 218mA for 12ns, 171mA for 8.8ns, and -184mA for 11.2ns.

Figure 36(a) The defect-free inverter circuit “good_inv2” on chip T26B-CJ. The difference with this set of inverters is the smaller transistor sizes, 2l by 5l for both the nmos and pmos.

Figure 36(c) The simulated data for the “good_inv2” inverter circuit. The first i_DDT pulse of 107mA lasts for 9ns. The second pulse of 214mA lasts for 20ns. As shown in the schematic, the inverter has its own dedicated power supply. This minimizes the effects of the padframe, the buffers, and other circuitry on the chip.

Figure 36(b) The Magic layout of the inverter circuit “good_inv2”. This figure shows the padframe on the left side, the buffers in the bottom right corner, and the actual inverter circuit connected to the middle two pads in the padframe.

Figure 36(d) The measured data for the inverter circuit “good_inv2”. The first i_DDT pulse ranges between plus and minus 250mA for 8.4ns. The second i_DDT pulse of negative 335mA lasts for 8ns. The notable feature of this measurement is the prominent ringing.

Figure 37(a) The schematic for the defective 2l by 5l inverter circuit “def_inv8” on chip T26B-CJ. The defect is a definite open in the power line. As in previous inverter circuits, the input is routed through a buffer before reaching the circuit under test.

Figure 37(c) The simulated data for the defective inverter circuit. The second trace shows the output pulled low (from the initial condition assumed to be high) and then not being able to be pulled high again. The corresponding i_DDT pulses reflect this. The initial pulse is a 100mA pulse lasting 5ns. All following are 44mA pulses lasting 4ns each.

Figure 37(b) The Magic layout for the defective inverter circuit “def_inv8”. The break in the power line can be clearly seen in the upper left side of the figure.

Figure 37(d) The measured data for the defective inverter circuit. This data relates to the third and fourth pulses of the simulated data. The first i_DDT pulse has a magnitude of 330mA. The second pulse has a magnitude of negative 370mA. Both pulses last approximately 6ns, not including the ringing following the transitions.

Figure 38(a) The schematic for the defective 2l by 5l inverter “def_inv9” on the chip T26B-CJ. This defect is an open gate on the pmos transistor, and has been represented in a rather unique way in the schematic. The end result is that the output should be pulled low decisively, but should have some level of trouble being pulled high.

Figure 38(c) The simulated data for “def_inv9”. Since the simulator assumes the floating gate is low, the pmos transistor is essentially on all the time. This causes a DC current of approximately 600mA when the output of the inverter should be low.

Figure 38(b) This figure shows an inverter circuit as seen under a microscope. The power and ground lines are routed from the left. The input and output lines are connected to the padframe at the bottom.

Figure 38(d) The measured data for the “def_inv9” circuit. In the fabricated circuit, the floating gate of the pmos transistor is not assumed to be at ground potential. Therefore it is not conducting. The measurements show there is a slight DC offset, but the i_DDT pulses are dominate with 360 and negative 380mA lasting 6.8 and 9.6ns, respectively.

Figure 39(a) The schematic for the defective 2l by 5l inverter circuit “def_inv9_1” from chip T26B-CJ. Notice that the output is tied to the power supply. This defect would be expected to cause a large transient pulse as well as a large quiescent current whenever the output should be at a low voltage.

Figure 39(c) The simulated data for the “def_inv9_1” circuit. As predicted, this defect causes a large i_DDQ of negative 1.09mA. 1 milliamp is 1000 times larger than 1 microamp. This large DC offset dominates the smaller i_DDT pulses seen at the points of transition.

Figure 39(b) The Magic layout for the defective inverter circuit “def_inv9_1”. The short between the output and the power supply rail is not detected by any means whenever the output of the inverter is high by design. However, when the output attempts to pull low, a conflict exists.

Figure 39(d) The measured data for the “def_inv9_1” inverter circuit. This measurement clearly shows a DC offset of negative 420mA. Also seen are the i_DDT pulses of 330mA for 7.6ns, and negative 280mA (measured from the DC offset level) for 6.4ns.

Figure 40(a) The schematic for the defective 2l by 5l inverter circuit “def_inv9_2” on chip T26B-CJ. Similar to the previous example, the output of the circuit is connected to the ground. Therefore no conflict should exist when the output is low by design. A definite conflict will exist when the output should be driven high.

Figure 40(c) The simulated data for “def_inv9_2”. The simulation shows that the middle part of the trace is normal, but the extremes give a large DC current of negative 410mA. As in the previous example, the i_DDT pulses are insignificant compared to the DC offset.

Figure 40(b) The Magic layout showing the defect implanted in “def_inv9_2”. The connection from the output to the ground rail can be seen clearly in the bottom right hand side of the figure. This type of defect should not cause a problem whenever the output of the device is driven low.

Figure 40(d) The measured data for “def_inv9_2”. This measurement follows the general trend of the simulation predictions with a DC offset of 195mA as well as some unwanted ringing. 415 and negative 380mA i_DDT pulses lasting 6.4 and 7.6ns respectively are also clearly seen.

Figure 41(a) The defective 2l by 5l inverter circuit “def_inv9_3” from the chip T26B-CJ. The defect shown is an open on the output of the device. The current difference in this case is expected to be minimal.

Figure 41(c) The simulated data for “def_inv9_3” on chip T26B-CJ. The first transition give an i_DDT 5.4ns pulse ranging between negative 34.4 and positive 42.9mA. The second gives a single i_DDT pulse of 45.2mA lasting approximately 4.2ns.

Figure 41(b) The Magic layout of the defective 2l by 5l inverter. The 3l break in the output is clearly visible in the figure. Again, since the output is only driving the padframe capacitance very little difference in the dynamic current pulse is expected.

Figure 41(d) The measured data for the defective inverter circuit. Except for some additional ringing, the measured data follows the general trends of the simulations. The first i_DDT pulse of 400mA lasts 6ns. The second pulse of negative 400mA lasts 7.6ns.

Figure 42(a) The schematic for the defect-free nor gate “good_nor1” on chip T26B-BV. As with the nand circuits, the inputs are routed through a set of buffers before reaching the gate.

Figure 42(c) The simulated data for the good nor circuit “nor_good1”. The output of the gate was inspected and functioned as designed. The i_DDT trace gives the following results:

-222mA with a 30ns recovery, 103mA for 8ns, 49mA for 5ns, 39mA for 4ns,

-219mA with a 30ns recovery, 102mA for 9ns, 41mA for 6ns, 44mA for 4ns.

Figure 42(b) The Magic software layout for the “good_nor1” circuit on chip T26B-BV. The padframe is at the top of the figure, and the buffers and circuit under test are shown with the traces at the bottom of the figure.

Figure 42(d) The measured data for the “good_nor1” circuit. This measurement correlates very well with the simulated data, especially with the large recovery periods. The data follows:

-284mA for 16ns with DC offset of

-147mA, 174mA for 4.2ns, 237mA for 10.4ns, -212mA for 8ns, -259mA for 12.8ns with DC offset of -184mA, 243mA for 8.8ns, 162mA for 9.6ns,

and finally -169mA for 8.8ns.

Figure 43(a) The schematic for the defective nor circuit “def_nor2” on chip T26B-BV. As always, the buffers and the padframe are given dedicated power supplies to eliminate interference with the circuit under test.

Figure 43(c) The simulated data for the “def_nor2” circuit. The beginning DC value of -.4mA gives way to the following i_DDT values:

128mA for 7ns, 49mA for 4ns, 49mA for 4ns, -228mA with a 30ns recovery, another -.4mA DC offset, another approach to zero, and finally the DC offset of -.4mA.

Figure 43(b) The Magic software layout for the “def_nor2” circuit on chip number T26B-BV. The floating pmos gate seen in the figure is assumed to have zero charge in the simulations, which explains the large DC offsets.

Figure 43(d) The measured i_DDT data for the “def_nor2” circuit. The profile seems to follow some of the simulation predictions.

-228mA for 8.8ns, 140mA for 8.8ns, 206mA for 9.6ns, -225mA for 11.2ns,

-190mA for 13.6ns, 175mA for 9.6ns, 165mA for 12ns, and -175mA for 11.2ns.

Figure 44(a) The schematic for the defective nor circuit “def_nor3” on chip T26B-BV. In this case the gate of the second pmos transistor is floating.

Figure 44(c) The simulated data for the “def_nor3” circuit. The 8 switches give the following 8 pulse characteristics:

39mA for 2ns, a large disturbance of 56mA for 16ns, a small pulse with a DC offset of 95mA, 36mA for 4ns, another DC offset of 95mA, another large disturbance of 83mA for 17ns, a pulse ranging from negative 33 to positive 43mA lasting approximately 4ns, and finally a 50mA pulse lasting 4ns.

Figure 44(b) The Magic layout for the defective nor circuit “def_nor3”.

Figure 44(d) The measured i_DDT data for the “def_nor3” circuit. In this case, the measured data does not seem to track the simulated data as well as some of the previous examples. The data follows:

-290mA for 11.2ns, 191mA for 12.8ns, 232mA for 12ns, 268mA for 9.6ns,

-156mA for 12.2ns, 271mA for 8.8ns, 168mA for 11.2ns, and finally -193mA for 8ns.

Figure 45(a) The schematic for the defective nor circuit “def_nor4” on chip T26B-BV. The defect is a floating gate on the nmos transistor.

Figure 45(c) The simulated i_DDT data for the “def_nor4” circuit. The values are: 109mA with a 30ns recovery, 114mA for 8ns, -37 to 54mA for 4ns, 43mA for 2ns, -232mA with a 30ns recovery, -45 to 45mA for 6ns, 112mA for 7ns, and finally 51mA for 2ns. Pulses lasting less than 4ns are considered meaningless noise and therefore not true i_DDTpulses.

Figure 45(b) The Magic software layout for the “def_nor4” circuit. Similar to the previous examples, the defect is a floating gate. However, this experiment focuses on the nmos transistor. The break in the trace is shown in the figure.

Figure 45(d) The measured data for the “def_nor4” circuit. This i_DDT trace matches the simulated data very closely in profile. The values are: -268mA for 14.4ns with a large recovery and ringing, 159mA for 12.8ns, 237mA for 8ns, -268mA for 11.2ns, -193mA for 9.6ns with a large recovery and ringing, 259mA for 12ns, -246mA for 8.8ns, and finally -160mA for 10.4ns.

Figure 46(a) The schematic for the defective nor gate “def_nor5” on chip T26B-BV. As in the previous example, the defect is located on the gate of an nmos transistor.

Figure 46(c) The simulated data for “def_nor5”. The 8 switches give the following 8 i_DDT pulses:

-193mA with a 30ns recovery, 11mA for 2ns, 99mA for 8ns, 37mA for 4ns,

-174mA for with a 30ns recovery, 85mA for 7ns, a range of –28 to 39mA for 5ns, and finally 40mA for 3ns.

Figure 46(b) The Magic software layout for the defective “def_nor5” circuit. This figure shows the broken nmos section of the circuit floating while the pmos section of the gate is securely connected to the driving input. Due to the common traits, this defect is expected to produce results similar to the previous example.

Figure 46(d) The measured i_DDT data for “def_nor5”. As before, these i_DDT traces correlate very well. The numbers are: -315mA for 11.2ns with large recovery and ringing, 203mA for 10.4ns, 231mA for 11.2ns, -275mA for 12ns, -243mA for 10.4ns with large recovery and ringing, 271mA for 10.4ns, 184mA for 12.8ns, and finally -218mA for 9.6ns.

Figure 47(a) The logic schematic for the adder circuit with negative logic, “Adder” on chip T24H-AR. Input A and Input B are also shown providing the inputs “00”, “01”, “11”, “10”, and returning to “00”.

Figure 47(c) Simulated waveforms for the negative logic circuit “Adder”. The first transition causes a 6ns i_DDT pulse with a magnitude of 96mA. The second one is a 25ns pulse of 193mA. The third and fourth are both 4ns disturbances of negative 42mA to 35mA respectively.

Figure 47(b) The “Adder” circuit layout in Magic detailing the connected padframe portion of the chip. The adder circuitry shown in the lower part of the figure is dwarfed by the padframe above it. The large squares at the top of the layout are the landings where the bond wires will connect the circuit to the package housing during the fabrication process

Figure 47(d) Measured data for the negative logic circuit “Adder”. The first and third transitions cause a pair of approximately 14.8ns i_DDT disturbances of approximately 730 and -770mA respectively, while the second and fourth pulses cause smaller 11ns ripples of 250 to negative 250mA.

Figure 48(a) The logic schematic for the adder circuit with negative logic, “Adder” on chip T24H-AR. As before, Input A and Input B are also shown. However, this example shows them providing inputs “00”, “10”, “11”, “01”, and finally returning to input “00”.

Figure 48(c) Additional simulated waveforms for the negative logic circuit “Adder”. The first and second transitions cause 6ns i_DDT pulses with ranges of –30 to 42mA. The third one is a 13ns pulse ranging between –66 and 88mA. The fourth and final disturbance is a large one of 200mA lasts approximately 38ns.

Figure 48(b) The layout of the circuit “Adder”. The control lines are shown routed to the right, while the power and ground lines are vertical.

Figure 48(d) The measured data for the “Adder” circuit. The first transition causes a 250mA i_DDT pulse for 12ns. The second, a 17.2ns pulse of 77mA. The third delivers an 11.6ns pulse of -250mA. Finally, the fourth pulse appears remarkable similar to the simulation with values of 21.2ns and -810mA.

Figure 49(a) Logic schematic for the adder circuit “Add1” on chip T24H-AR. The defect highlighted by the broken lines is a gap in poly material. The input signals are also shown. Input “B” is kept HIGH.

Figure 49(c) Simulated waveforms for the adder circuit “Add1”. The DC values start and end at -132mA, approaching 0mA between the points of transition. The first switch gives a 6ns i_DDT pulse with a minimum of -163mA and a maximum of –80.9mA. The second switch gives a 5ns pulse between 46.6mA and 9.92mA.

Figure 49(b) Circuit layout in Magic of the adder circuit “Add1”. Although difficult to detect in the figure, the 1-l defect is placed in poly material and labeled with the words “defside1” and “defside2”.

Figure 49(d) Measured waveforms for the adder circuit “Add1”. With a DC value of 340mA, the first switch gives a 9.2ns 490mA i_DDT pulse in the positive direction. Unlike the simulations, the period between the pulses appears to approach the DC value without an offset. The second pulse gives a downward pulse of 530mA lasting 10.4ns.

Figure 50(a) Logic schematic for the defect-free adder circuit “Adder” on chip T24H-AR. The input signals used in the previous example are also shown. Again, Input “B” is kept HIGH for comparison with the previous example.

Figure 50(c) Simulated data for the defect-free adder circuit “Adder”. With an external DC value of 152mA, the switches cause 108 and -136mA i_DDT pulses lasting 14 and 12ns, respectively. The DC value between the switches is 0.8mA or in other words, a fraction of a microamp. For all intents and purposes, it can be considered to be zero.

Figure 50(b) This shows the “Adder” circuit as seen under a video microscope. This figure is the physical result of the circuit layout shown in the previous example.

Figure 50(d) The Measured data for the defect-free adder circuit “Adder” on chip T24H-AR. The first switch causes an 810mA i_DDT disturbance lasting for 15.2ns, while the second switch causes one of -830mA lasting for approximately 14.4ns. The measurements do not show the DC offset seen in the simulations.

Figure 51(a) Logic schematic for the adder circuit “Add1” on chip T24H-AR. As before, the defect highlighted by the broken lines is a gap in poly material. The input signals are also shown. In this case, input “B” is kept LOW.

Figure 51(c) Simulated waveforms for the adder circuit “Add1”. The DC value of approximately 0mA is interrupted at the points of transition by pulses that swing in both the positive and negative directions. The first switch gives a 14ns pulse with a minimum of –30.7mA and a maximum of 35mA. The second switch gives a 39ns disturbance that stretches between –35.0mA and a positive 24.1mA.

Figure 51(b) Circuit layout in Magic of the adder circuit “Add1”. As previously discussed, the 1-l defect is placed in poly material and labeled with the words “defside1” and “defside2”. As mentioned earlier, this circuit provides negative logic. Therefore the inverters on the “Carry” and “Out” outputs were not needed.

Figure 51(d) Measured waveforms for the adder circuit “Add1”. With a DC value estimated to be 245mA, the first switch gives a 9.6ns 190mA i_DDT pulse in the positive direction, with a slight undershoot on the return. The second transition gives a downward i_DDT pulse of 140mA lasting approximately 10ns.

Figure 52(a) Logic schematic for the adder circuit “Adder” on chip T24H-AR. The input signals are also shown. In this case, input “B” is kept LOW for comparison with the previous example.

Figure 52(c) The simulated waves for the circuit “Adder”. The first switch gives a 96mA i_DDT pulse with a width of 17.2ns. The second switch gives an impressive pulse of 198mA with an equally impressive width of 46ns.

Figure 52(b) This figure shows another view of the defect-free “Adder” circuit underneath a video microscope. The larger of the traces shown represent the materials “Metal1” and “Metal2”. The smaller details make up the transistors using “Ndif”, “Pdif”, and “Poly”.

Figure 52(d) The measured waves for the “Adder” circuit. The first switch gives an i_DDT disturbance of 820mA with a duration of 19.2ns. The second switch gives a pulse of -850mA lasting approximately 18ns. The second pulse closely resembles the simulated data.

Figure 53(a) The logic schematic for the adder circuit with negative logic, “Add2” on chip T24H-AR. Input A must be kept LOW to sensitize the circuit to the defect. Input B is toggled from low to high, and then back to low.

Figure 53(c) The simulated data for the “Add2” circuit. The first pulse from the defective adder circuit gives an i_DDT disturbance lasting approximately 6ns with a swing of negative 31 to positive 40.8mA. The second disturbance lasts approximately 7ns and gives a swing of negative 32 to positive 26mA.

Figure 53(b) The Magic layout of the defective adder circuit “Add2”. The defect can be seen near the lower left hand corner of the figure. In this case the defect is a 1-l open in poly material. Since the defect in this circuit was implanted further in the circuit, special consideration had to be given to the test vectors.

Figure 53(d) Measured data for the “Add2” defective adder circuit. The first transition gives an 8.8ns i_DDT disturbance ranging from negative 95 to positive 225mA. The falling transition gives an 11.2ns disturbance at negative 195mA. Although the magnitudes differ, the general patterns of the traces are similar.

Figure 54(a) The logic schematic for the adder circuit with negative logic, “Add2” on chip T24H-AR. As before in the defective circuit, Input A must be kept LOW to sensitize the circuit to the defect. Input B is toggled from low to high, and then back to low.

Figure 54(c) The simulated data for the defect-free adder circuit “Add2”. The first transition gives a 9ns i_DDT disturbance peaking at 78mA. The second transition gives a large 27ns disturbance reaching negative 199mA.

Figure 54(b) A slightly larger version of the familiar adder circuit layout in Magic. This “zoomed-in” view shows some of the details of this circuit.

Figure 54(d) The measured data for the defect-free adder circuit “Add2”. The first i_DDT pulse ranges from negative 260 to positive 260mA for 10.8ns. The second 12.8ns i_DDT pulse reaches negative 260mA.

Figure 55(a) The logic schematic for the defect-free Or-And-Invert circuit “good1_oai21” on chip T26B-CL. The inputs to the gate are routed through buffers. The transistor sizes are 2l x 10l for pmos and 2l x 5l for nmos.

Figure 55(c) The simulated data for the defect-free Or-And-Invert OAI21 circuit “good1_oai21”. Switching Input A1 causes a disturbance of 7ns with a magnitude of 103mA followed by a negative 104mA pulse with a 30ns recovery time.

Figure 55(b) The Magic layout of the defect-free Or-And-Invert circuit “good1_oai21”. The top part of the figure shows the padframe. The bottom section shows the layout of the buffers and the OAI21 circuit. The power and ground connections shown connecting all of the small clusters of devices are noticeably larger than the signal traces.

Figure 55(d) The measured data for the defect-free OAI21 circuit. Input A1 is shown toggling from low to high, and then back to low. The i_DDT pulses created are 170mA for 6.2ns and -140mA for 4.8ns. The long recovery period seen in the simulation is not present in the measured data.

Figure 56(a) The transistor level schematic for the defect-free Or-And-Invert circuit “good1_oai21” on chip number T26B-CL. The buffers are represented at the gate level. This is the same circuit shown in the previous example with different stimuli.

Figure 56(c) The simulated data for the defect-free OAI21 circuit. The first i_DDT pulse of 103mA lasts 8.2ns, while the second of -212mA has a 30ns recovery time. As expected, this result is very similar to the previous example.

Figure 56(b) The Magic layout for the defect-free Or-And-Invert 21 circuit “good1_oai21”. The previous example showed the circuit surrounded by the padframe and other circuitry. This figure shows a zoomed-in view of the OAI circuit.

Figure 56(d) The measured data for the defect-free OAI21 circuit. As Input B2 switches, two i_DDT pulses of 230 and negative 215mA are created lasting 5 and 5.8ns, respectively. Deviations from the previous example can be explained in part by the circuit layout shown above.

Figure 57(a) The transistor level schematic for the defect-free “good1_oai21” circuit on T26B-CL. To make this image a bit easier to read, the power and ground connections are represented with the usual arrow and ground symbols.

Figure 57(c) The simulated data for the “good1_oai21” circuit. As Input C3 switches, the resulting i_DDT pulses are 103mA for 8ns and -275mA with the usual 30ns recovery seen previously.

Figure 57(b) The Magic layout of the buffer circuit used on the “good1_oai21” circuit. In most cases a buffer is comprised of 2 inverters in series. In this case, a single inverter is used to drive dual inverters connected in parallel. The end result is a buffer that can drive heavier loads. This figure shows the input to the first inverter routed from the right. The output then connects to the dual inverters. The buffer output exits the figure at the top center.

Figure 57(d) The measured data for “good1_oai21”. The first i_DDT pulse of 190mA lasts 6.6ns. The second pulse of negative 175mA lasts 5.4ns. Again, the large recovery time shown in the simulations is not present in this data.

Figure 58(a) The transistor level schematic for the defective Or-And-Invert circuit “def1_oai21” on chip T26B-CL. The open defect of a missing via is shown. As before, the transistor sizes are 2l x 10l for the pmos and 2l x 5l for the nmos.

Figure 58(c) The simulated data for the defective “def1_oai21” circuit. The first transition causes an i_DDT pulse ranging between –25 and +29mA for 5ns. The second causes a 32mA disturbance for approximately 4ns.

Figure 58(b) The Magic software layout for the defective OAI 21 circuit. This figure shows the missing via between the materials in the lower part of the picture. In this case, the gates of the transistors are connected together, and therefore have the same voltage applied to them. However, this voltage can not be controlled by the inputs because of the defect.

Figure 58(d) The measured data for the “def1_oai21” circuit. This defect causes noisy i_DDT pulses of positive and negative 110mA lasting 6.8 and 5ns, respectively. This result is not surprising considering the type of defect.

Figure 59(a) The transistor level schematic for the defective OAI 21 circuit “def2_oai21” on chip number T26B-CL. Similar to the previous defect, the gates of the pmos and nmos are connected to each other but can not be driven high or low.

Figure 59(c) The simulated data for “def2_oai21” on chip T26B-CL. Similar to the previous example, the first i_DDT pulse ranges from –25 to +30mA for 5ns. The second gives 33mA for 4ns.

Figure 59(b) The Magic software layout for “def2_oai21”. The missing via open defect can be seen at the transition of the materials at the very bottom of the figure. Because the voltage on both gates is virtually identical, the possibility of both transistors being on is eliminated. Therefore, the i_DDT pulses in the simulations and the measurements are expected to be minimal.

Figure 59(d) The measured data for the “def2_oai21” circuit. The first i_DDT pulse reaches 215mA for 7.2ns. The second disturbance of -210mA lasts 6.4ns.

Figure 60(a) The transistor schematic for the defective circuit “def3_oai21”on chip T26B-CL. Once again the defect is an open between the buffered input and the gates of the transistors. Similar results are expected because of the nature of the defect.

Figure 60(c) The simulated data for the defective “def3_oai21” circuit. Similar to the previous examples, the first i_DDT disturbance ranges from –32 to +40mA for 5ns. The second one gives 41mA for 4ns.

Figure 60(b) The Magic layout for the “def3_oai21” circuit. The missing via is located at the overlap of the trace shown on the left hand side of the figure. Again, the gates of the nmos and pmos transistors are connected to each other but disconnected from the trace used to control them.

Figure 60(d) The measured data for the defective “def3_oai21” circuit. The first transition causes an i_DDT disturbance of 170mA for 6.6ns. The second switch causes a pulse of -175mA lasting approximately 5.2ns.

Figure 61(a) The transistor level schematic for the defective OAI21 circuit “def4_oai21” on chip T26B-CL. This defect differs from the previous examples since only one of the transistors is uncontrolled.

Figure 61(c) The first set of simulated data for the defective “def4_oai21” circuit. This simulation shows that the defective pmos transistor is stuck “on” and provides a DC current of -0.4mA.

Figure 61(b) The Magic layout for the defective “def4_oai21” circuit. The defect shown in this figure is a disconnect on the pmos transistor. The nmos transistor still operates as usual. Since the simulator assumes there is no charge on the floating material, the gate is virtually grounded and stuck “on”. For comparison, another run of this circuit will be made with a resistor charging the floating gate.

Figure 61(d) The measured data for the “def4_oai21” circuit. This i_DDT trace differs from the simulation. The first switch causes an i_DDT pulse of 210mA for 5.8ns. The second, a negative pulse of 205mA for 5.2ns.

Figure 62(a) The transistor level schematic for the defective OAI21 circuit “def4_oai21” on chip T26B-CL. This shows the same defect used in the previous example.

Figure 62(c) The simulated data for the “def4_oai21” circuit. In this simulation, a 1k resistor pulled the floating gate away from the default ground. These results appear to be more representative of the measured results. The resulting i_DDT disturbances are 111mA for 5.3ns and 52mA for 3ns.

Figure 62(b) The Magic software layout for the “def4_oai21” circuit. This defective circuit was simulated in the previous example with the floating gate assumed to be grounded. This seems to be a valid assumption if the gate gathers no charge. However in practice, the gate voltage is not truly grounded, and therefore the pmos transistor is not “on”.

Figure 62(d) The measured results for the defective “def4_oai21” circuit. These results agree in profile with the simulation. The first i_DDT pulse of 210mA lasts for 5.8ns. The second i_DDT pulse of -205mA lasts for 5.2ns.

Figure 63(a) The transistor level schematic for the defective Or-And-Invert circuit “def5_oai21” on chip T26B-CL. Similar to the circuit shown in the previous example, the gate of one of the pmos transistors is floating. The nmos transistor functions correctly.

Figure 63(c) The simulated data for the “def5_oai21” circuit. The floating gate assumed to be grounded gives way to the large DC offset current of 0.48mA. Another run will be made which forces this gate to float to a higher potential.

Figure 63(b) The Magic layout of the defective “def5_oai21” circuit. Similar to the previous example, the floating gate on the pmos transistor is assumed to be at zero potential by the simulator. Therefore the simulation does not provide realistic results in this case. Another simulation with a resistor pulling the gate voltage higher will be given in the next example.

Figure 63(d) The measured data for the “def5_oai21” circuit. The first i_DDT pulse of 90mA lasts 5.8ns. The second pulse of 100mA lasts 5.4ns.

Figure 64(a) The schematic for the “def5_oai21” circuit showing the transistor layout and the defect location. As before, the buffers are shown with their gate level representation. The defect is an open on the pmos associated with Input B2.

Figure 64(c) The simulated data for the “def5_oai21” circuit. With the addition of a 1k resistor pulling the floating gate to a high voltage, the first i_DDT pulse gives –40 to 48mA for 5ns. The second i_DDT pulse gives 55mA for approximately 4ns.

Figure 64(b) The Magic software layout for the “def5_oai21” circuit. Like the previous example, this figure shows the broken trace between the pmos and nmos transistors. This example gives the simulation results that are more realistic than the previous run. This is bolstered by the measured data given in the figure below.

Figure 64(d) The measured data for the “def5_oai21” circuit. The first switch gives an i_DDT pulse of 90mA for 5.8ns. The second switch gives an i_DDT pulse of 100mA for 5.4ns. These measurements do not appear to be clean pulses, but rather large disturbances.

Figure 65(a) The transistor level schematic for the defective OAI 21 circuit “def6_oai21” on chip T26B-CL. This defect is an open on the gate of the pmos transistor associated with Input C3. Once again, the nmos transistor functions normally.

Figure 65(c) The simulated data for “def6_oai21”. As in previous examples, the simulation of this defect causes a DC current. In this specific case, it is very large, 0.7mA. This is probably due to the defective transistor not having any other component in series.

Figure 65(b) The Magic software layout for the defective “def6_oai21” circuit. As in the previous examples, the pmos is disconnected from the functioning nmos. This figure shows a break in the poly near the center of the picture. To realistically simulated this defect, another run will be made with the addition of a resistor.

Figure 65(d) The measured data for the “def6_oai21” circuit. As seen in previous examples, the pulses are not clearly defined spikes, but are rolling waves. The first significant disturbance is measured to be an i_DDT pulse of 105mA for 6.4ns. The second one is a

-100mA wave which also lasts for 6.4ns.

Figure 66(a) The schematic of the defective OAI21 circuit “def6_oai21” on chip T26B-CL. This schematic shows the additional resistor used to pull the gate away from virtual ground in the simulations.

Figure 66(c) The simulated data for the defective “def6_oai21” circuit. Similar to the previous examples of this nature, the addition of a 1k resistor gives more realistic results. The first i_DDT pulse ranges from –33 to 39mA for 3ns. The second i_DDT pulse is 40mA for 3ns.

Figure 66(b) The layout of the defective “def6_oai21” circuit. Once again, the open defect affects the pmos transistor and not the nmos transistor. This can be seen in the picture. Also visible in the picture is the obvious size difference in the transistors. The pmos devices shown at the top are twice the size of the nmos units at the bottom.

Figure 66(d) The measured data for the “def6_oai21” circuit. As before, these measured results form a better match than the previous runs. The first i_DDT pulse is a 105mA wave lasting 6.4ns. The second i_DDT pulse is a negative wave of 100mA lasting 6.4ns.

Figure 67(a) The transistor level schematic for the defective “def7_oai21” circuit found on chip T26B-CL. This defect is the opposite of the previous few examples. In this case, the nmos transistor is the one that is affected by the defect. The pmos transistor functions normally.

Figure 67(c) The simulated data for the “def7_oai21” circuit. The first switch gives a range of –25 to +34mA for 5ns. The second gives an i_DDT pulse of 29mA for 5ns.

Figure 67(b) The layout of the defective “def7_oai21” circuit shown in Magic software. The defect shown near the center of the figure shows the break in the material. It also represents the control line from the input being rerouted in from the right. This new control line allows the pmos transistor to function normally while the nmos transistor is undriven.

Figure 67(d) The measured data for the “def7_oai21” circuit. The first i_DDT pulse is 200mA for 5.6ns. The second i_DDT pulse is -185mA for 6.4ns.

Figure 68(a) The transistor level schematic for the defective “def8_oai21” circuit on chip T26B-CL. In this case, the defect is an open on the nmos transistor associated with Input B2. The test input vectors show Input B2 toggling from low to high and back to low.

Figure 68(c) The simulated data for “def8_oai21”. The first i_DDT pulse ranges from –25 to +30mA for 5ns. The second i_DDT pulse gives 32mA for 5ns.

Figure 68(b) This figure shows some of the bond wires used on the 40-pin package housing circuits similar to the defective “def8_oai21” on T26B-CL. This picture was taken using the video microscope in the cleanroom located in the Cameron Applied Research Center.

Figure 68(d) The measured i_DDT pulses for the “def8_oai21” circuit. The first i_DDT pulse gives 100mA for 5.6ns. The second one gives -105mA for 5.4ns. Again, these pulses are not well defined.

Figure 69(a) The schematic for the defective OAI 21 circuit “def9_oai21” on chip T26B-CL. Once again, the defect is an open placed on the gate of an nmos transistor. In this case, the transistor is the one associated with Input C3.

Figure 69(c) The simulated i_DDT pulses for “def9_oai21”. The first pulse gives a range from –33 to +43mA for 5ns. The second one gives 36mA for 4ns.

Figure 69(b) The Magic software layout for the defective Or-And-Invert circuit “def9_oai21”. The trace shown on the left hand side of the figure indicates that the pmos transistor is connected as designed. The gate of the nmos on the bottom is clearly floating. The defect implanted in this circuit should provide interesting results since its location is between ground and the rest of the circuit.

Figure 69(d) The measured i_DDT pulses for the “def9_oai21” circuit. The first pulse yields 140mA for 5.6ns, again with some noise and moderate ringing. The final pulse gives -105mA for 5.4ns.

CHAPTER 5: CONCLUSIONS AND FUTURE WORK

The goal of this document is to provide both tools and information to advance the field of electronics testing using the i_DDTtesting method. Because the fabrication of a chip is such a complex and resource intensive process, errors are easily created and very costly. In addition to these problems, the shrinking technology allows a greater number of devices within any given square millimeter of a silicon wafer. This leads to a larger number of devices per chip that require verification. The fabrication technology is growing faster than the technology used to test the products. One partial solution to these problems is to add i_DDTtesting to the battery of testing already performed by manufacturers.

The Toggle algorithm outlines a method of targeting a specific device within a gate level schematic. The gates along the path from the primary input to the target are set to their sensitized states. The surrounding gates are set to their desensitized states in order to minimize the required number of gate switches. The computer code written to implement this code proved that the algorithm is valid. Although other software packages can provide this information, this algorithm does operate in a unique way. The code allows a great deal of flexibility in the number of gate inputs. The Toggle algorithm also offers a second “brute force” method for smaller circuits.

The Mapper CAD algorithm details the steps necessary to analyze a logic level circuit with transistor level defects. To accomplish this task, the algorithm must consult a

library of faults. This library details the logic level gates and the defects implanted in them. The defects are mapped from the transistor level into the gate level circuit. Depending on the type and the location of these defects, the faulty circuit may provide a different gate level switching profile than the defect-free circuit. The Mapper CAD algorithm observes this switching profile for the defective circuit, automatically replaces the defective gates with a defect-free version, and repeats the observation using the same input conditions. The end result is a comparison of the switching profile of a defective circuit compared to the switching profile of the defect-free version of the same circuit.

The computer code implementation of the Mapper CAD algorithm has shown that the algorithm is valid. In fact, the code has been debugged to allow several conditions that normally would be considered anomalous. For example, the code allows a single node to branch to multiple inputs of the same gate. Also, some error checking is used in both programs to prevent any missteps and to allow a graceful recovery from many common user mistakes. Another useful addition is fact that undetermined variables can be assigned to primary inputs. This allows a great deal of flexibility, and is particularly useful when a smaller portion of a larger circuit needs to be controlled and closely observed.

The measured data provides a wealth of information. Each page focuses on one test circuit, and documents the circuit schematic and the transistor layout. Also provided are the circuit name, the circuit number, the pin numbers, and the inputs used to stimulate the circuit. Each of the figures showing measured i_DDT data is an actual screen shot of a careful measurement. These measurements have been made using superior laboratory equipment with high speed capabilities and high bandwidth probes.

The simulations of the i_DDT data attempt to mimic the measured data by including the capacitive, resistive, and inductive affects of the circuit package, as well as other affects of the probes and other measurement equipment. In some cases, the traces of the measurements and the traces of the simulations seem to diverge. However, some of the simulations appear to be strikingly similar to the measured i_DDT data. The diversity of these simple “building block” circuits and the various implanted defects work together to provide a valuable preliminary study of defects, their fault models, and the associated i_DDT current measurements.

Future work in this area would include some refining of the algorithms used to create the design tools. Additional gates need to be added to the library. Compound gates larger than the AOI21 and the OAI21 can be analyzed and their truth tables coded. Many other circuits need to be measured and documented. Since small circuits give small differences in i_DDT currents, perhaps larger circuits can provide some dramatic i_DDT current measurements.

Fortunately, the nature of this research easily lends itself to continuation. Even if the measured i_DDT responses of all circuits ever created were physically measured and documented at this point in time, future research would be needed in this area. Because the i_DDT parameter is highly dependent on the fabrication technology, new circuit fabrications will require additional testing. In fact, a new set of measurements will be required even if the exact same circuit is simply created with a new technology.

The software programs coded to implement the algorithms also present a virtually endless project. Because the algorithms use expandable libraries of gates, the computer code can never be considered complete. This is not a weakness, but rather a strength. For example, if a future technology allows a CMOS AND gate to have a dozen inputs, the computer code library can be updated to adapt to this change. These software tools along with the measured information presented in this document provide practical tools and useful information to advance the study of i_DDT testing.

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APPENDIX A: MAPPER CAD LIBRARY

This section documents the gates available in the Mapper CAD library. The defect-free versions of the gates are represented by their standard gate level logic symbols. The defective versions are shown at the transistor level with the defects (or the equivalent defects) marked on the schematic. Because in many cases the truth tables contain repetitive information, abbreviated tables are given whenever possible.

Figure 70 The NAND Gate. This gate is defect-free. This NAND gate can be used as a 2, 3, or 4-input device.

Table 14 The Truth Table for the defect-free NAND Gate. An undetermined input to the NAND gate will cause the output to be undetermined if all of the other inputs are 1's. If any of the inputs are 0's, then the output will be a 1, even if one or more of the inputs is a definite 1 or an undetermined value.

A	B	C	D	Z
0	0	0	0	1
0	0	0	1	1
0	0	1	0	1
0	0	1	1	1
0	1	0	0	1
0	1	0	1	1
0	1	1	0	1
0	1	1	1	1
1	0	0	0	1
1	0	0	1	1
1	0	1	0	1
1	0	1	1	1
1	1	0	0	1
1	1	0	1	1
1	1	1	0	1
1	1	1	1	0
W	0	x	x	1
W	1	1	1	W

Figure 71 The Defective NAND Gate circuit “DNAND1”. The defect represented in this case is an open on the output line. However, an open on one of the inputs is an equivalent defect. Additionally, a resistive defect that ties the output or input to an undetermined state is an equivalent defect. This is true whether the open in present on the line or not! Although input A is shown to be the possible location for the defect, the result is the same for inputs B, C, and D.

Table 15 The Truth Table for the Defective NAND Gate circuit “DNAND1”. With an undetermined input or an undetermined output, the output is undetermined regardless of the inputs.

A	B	C	D	Z
x	x	x	x	W

Figure 72 The Defective NAND Gate Circuit “DNAND2”. The transistor level defect in this gate is an open on the pmos transistor of input A.

Table 16 The Truth Table for the Defective NAND Gate circuit “DNAND2”. In this case, any input (other than the defective input A) can pull the gate to a high level as long as the input is a 0.

A	B	C	D	Z
0	0	0	0	1
0	0	0	1	1
0	0	1	0	1
0	0	1	1	1
0	1	0	0	1
0	1	0	1	1
0	1	1	0	1
0	1	1	1	A
1	0	0	0	1
1	0	0	1	1
1	0	1	0	1
1	0	1	1	1
1	1	0	0	1
1	1	0	1	1
1	1	1	0	1
1	1	1	1	0
x	W	0	x	1
x	W	1	1	W

Figure 73 The Defective NAND Gate Circuit “DNAND3”. The transistor level defect in this gate is an open on the nmos transistor of input A.

Table 17 The Truth Table for the Defective NAND Gate circuit “DNAND3”. In this case, any input can pull the gate to a high level as long as the input is a 0. However, none of the inputs can pull the output low.

A	B	C	D	Z
0	0	0	0	1
0	0	0	1	1
0	0	1	0	1
0	0	1	1	1
0	1	0	0	1
0	1	0	1	1
0	1	1	0	1
0	1	1	1	1
1	0	0	0	1
1	0	0	1	1
1	0	1	0	1
1	0	1	1	1
1	1	0	0	1
1	1	0	1	1
1	1	1	0	1
1	1	1	1	V
0	W	x	x	1
x	W	1	1	W

Figure 74 The NOR Gate. This gate is defect-free. This NOR gate can be used as a 2, 3, or 4-input device.

Table 18 The Abbreviated Truth Table for the NOR Gate. If any of the inputs are 1, then the output is zero. If an input is undefined, the output will pass if no other input is 1.

A	B	C	D	Z
0	0	0	0	1
1	x	x	x	0
W	1	x	x	0
W	0	0	0	W

Figure 75 The Defective NOR Gate circuit “DNOR1”. The defect represented in this case is an open on the output line. However, an open on one of the inputs is an equivalent defect. As seen before with the defective NAND gate, a resistive defect that ties the output or input to an undetermined state is also an equivalent defect. This is true whether the open in present on the line or not! Although input A is shown to be the possible location for the defect, the result is the same if the defect is locate on inputs B, C, or D.

Table 19 The Truth Table for the Defective NOR Gate circuit “DNOR1”. The output is undetermined regardless of the inputs.

A	B	C	D	Z
x	x	x	x	W

Figure 76 The Defective NOR circuit “DNOR2”. The defect in this case is an open on the pmos transistor associated with input A. Because any defect on this transistor would give the same logical performance, this open would be equivalent to any other open on the source or the drain of the transistor in question.

Table 20 The Abbreviated Truth Table for the Defective NOR Gate “DNOR2”. If all inputs are 0, then the output will unsuccessfully attempt to pull high. If any of the inputs are 1, then the output is zero. If an input is undefined, the output will pass if no other input is 1. If another input is 1, then of course the output will be a 0, as previously stated.

A	B	C	D	Z
0	0	0	0	A
1	x	x	x	0
W	1	x	x	0
W	W	0	0	W

Figure 77 The Defective NOR Circuit “DNOR3”. The problem implanted inside this gate is a defective nmos transistor on input A.

Table 21 The abbreviated Truth Table for the Defective NOR Circuit “DNOR3”. If any input is 1, the output is either 0, or is trying to reach 0 in the case of input A being 1. All inputs being 0 except for an undetermined will provide an undetermined output.

A	B	C	D	Z
0	0	0	0	1
1	1	x	x	0
1	0	0	0	V
W	W	0	0	W

Figure 78 The Defect-free Inverter Circuit “INV”. This gate inverts the logic level of the input. If the input is undetermined, then the output is undetermined.

Table 22 The Truth Table for the Defect-free Inverter Circuit “INV”.

A	Z
0	1
1	0
W	W

Figure 79 The Defective Inverter Circuit “DINV1”. This circuit provides an undetermined output under all conditions. Either an open or a resistive defect located on either the input or the output provide results that can not be predicted.

Table 23 The Truth Table for the Devective Inverter Circuit “DINV1”.

A	Z
0	W
1	W
W	W

Figure 80 The Defective Inverter Circuit “DINV2”. This circuit provides an undetermined output when the output is trying to be pulled high. The defective pmos transistor will not allow the correct output when the input is 0. However, the output does provide a 0 when the input is 1.

Table 24 The Truth Table for the Defective Inverter Circuit “DINV2”.

A	Z
0	A
1	0
W	W

Figure 81 The Defective Inverter Circuit “DINV3”. This circuit provides an undetermined output when the output is trying to be pulled low. The defective nmos transistor will not allow the correct output when the input is 1. However, the output does provide a 1 when the input is 0.

Table 25 The Truth Table for the Defective Inverter Circuit “DINV3”.

A	Z
0	1
1	V
W	W

Figure 82 The Defect-free AOI21 Circuit “AOI21”. Unlike the situations encountered with the previous circuits, the inputs to this compound gate are not interchangeable. Previously the name “input A” could be swapped with “input B” to give identical logical results. This luxury is no longer available with the remaining circuits in this library.

Table 26 The Truth Table for the Defect-free AOI21 Circuit “AOI21”.

A	B	C	Z
0	0	0	1
0	0	1	0
0	1	0	1
0	1	1	0
1	0	0	1
1	0	1	0
1	1	0	0
1	1	1	0

(continued on the next page)

Table 26 (continued)

A	B	C	Z
W	0	0	1
W	0	1	0
W	1	0	W
W	1	1	0
0	W	0	1
0	W	1	0
1	W	0	W
1	W	1	0
0	0	W	W
0	1	W	W
1	0	W	W
1	1	W	0

W	0	W	W
W	W	0	W
W	1	W	W
W	W	1	0
0	W	W	W
1	W	W	W

W	W	W	W

Figure 83 The Defective AOI21 circuit “DAOI211”. The open output (or equivalent resistive defect) gives an unknown values for any combination of inputs.

Table 27 The Truth Table for the Defective AOI21 circuit “DAOI211”.

A	B	C	Z
x	x	x	W

Figure 84 The Defective AOI21 Circuit “DAOI212”. The open defect on the C input prevents the output from ever being pulled to a definitive high level.

Table 28 The Truth Table for the Defective AOI21 Circuit “DAOI212”.

A	B	C	Z
0	0	0	W
0	0	1	W
0	1	0	W
0	1	1	W
1	0	0	W
1	0	1	W
1	1	0	0
1	1	1	0

W	0	0	W
W	0	1	W
W	1	0	W
W	1	1	W
0	W	0	W
0	W	1	W
1	W	0	W
1	W	1	W
0	0	W	W
0	1	W	W
1	0	W	W
1	1	W	0

W	0	W	W
W	W	0	W
W	1	W	W
W	W	1	W
0	W	W	W
1	W	W	W

W	W	W	W

Figure 85 The Defective AOI21 Circuit “DAOI213”. The open defect on the pmos of the C input prevents the output from ever being pulled to a definitive high level. However, the C input can still provide a definite pull to ground.

Table 29 The Truth Table for the Defective AOI21 Circuit “DAOI213”.

A	B	C	Z
0	0	0	A
0	0	1	0
0	1	0	A
0	1	1	0
1	0	0	A
1	0	1	0
1	1	0	0
1	1	1	0

W	0	0	W
W	0	1	0
W	1	0	W
W	1	1	0
0	W	0	W
0	W	1	0
1	W	0	W
1	W	1	0
0	0	W	W
0	1	W	W
1	0	W	W
1	1	W	0

W	0	W	W
W	W	0	W
W	1	W	W
W	W	1	0
0	W	W	W
1	W	W	W

W	W	W	W

Figure 86 The Defective AOI21 Circuit “DAOI214”. The open defect on this nmos transistor prevents the lone C input from ever pulling the output to a definitive low level.

Table 30 The Truth Table for the Defective AOI21 Circuit “DAOI214”.

A	B	C	Z
0	0	0	1
0	0	1	V
0	1	0	1
0	1	1	V
1	0	0	1
1	0	1	V
1	1	0	0
1	1	1	0

W	0	0	1
W	0	1	V
W	1	0	W
W	1	1	V
0	W	0	1
0	W	1	V
1	W	0	W
1	W	1	W
0	0	W	W
0	1	W	W
1	0	W	W
1	1	W	0

W	0	W	W
W	W	0	W
W	1	W	W
W	W	1	W
0	W	W	W
1	W	W	W

W	W	W	W

Figure 87 The Defective AOI21 Circuit “DAOI215”. The open defect on the A input prevents this complimentary transistor pair from functioning properly.

Table 31 The Truth Table for the Defective AOI21 Circuit “DAOI215”.

A	B	C	Z
0	0	0	1
0	0	1	0
0	1	0	A
0	1	1	0
1	0	0	1
1	0	1	0
1	1	0	V
1	1	1	0

W	0	0	1
W	0	1	0
W	1	0	W
W	1	1	0
0	W	0	W
0	W	1	0
1	W	0	W
1	W	1	0
0	0	W	W
0	1	W	W
1	0	W	W
1	1	W	W

W	0	W	W
W	W	0	W
W	1	W	W
W	W	1	0
0	W	W	W
1	W	W	W

W	W	W	W

Figure 88 The Defective AOI21 Circuit “DAOI216”. The open defect on the pmos transistor associated with the A input prevents this gate from operating properly under some input conditions.

Table 32 The Truth Table for the Defective AOI21 Circuit “DAOI216”

A	B	C	Z
0	0	0	1
0	0	1	0
0	1	0	A
0	1	1	0
1	0	0	1
1	0	1	0
1	1	0	0
1	1	1	0

W	0	0	1
W	0	1	0
W	1	0	W
W	1	1	0
0	W	0	W
0	W	1	0
1	W	0	W
1	W	1	0
0	0	W	W
0	1	W	W
1	0	W	W
1	1	W	0

W	0	W	W
W	W	0	W
W	1	W	W
W	W	1	0
0	W	W	W
1	W	W	W

W	W	W	W

Figure 89 The Defective AOI21 Circuit “DAOI217”. The open defect on the nmos transistor associated with the A input prevents this gate from operating properly under some input conditions.

Table 33 The Truth Table for the Defective AOI21 Circuit “DAOI216

A	B	C	Z
0	0	0	1
0	0	1	0
0	1	0	1
0	1	1	0
1	0	0	1
1	0	1	0
1	1	0	V
1	1	1	0

W	0	0	1
W	0	1	0
W	1	0	W
W	1	1	0
0	W	0	1
0	W	1	0
1	W	0	W
1	W	1	0
0	0	W	W
0	1	W	W
1	0	W	W
1	1	W	W

W	0	W	W
W	W	0	W
W	1	W	W
W	W	1	0
0	W	W	W
1	W	W	W

W	W	W	W

Figure 90 The Defect-free Or-And-Invert-21 Circuit “OAI21”. As Before, the inputs to this compound gate are not interchangeable.

Table 34 The Truth Table for the Defect-free OAI21 Circuit “OAI21”.

A	B	C	Z
0	0	0	1
0	0	1	1
0	1	0	1
0	1	1	0
1	0	0	1
1	0	1	0
1	1	0	1
1	1	1	0

W	0	0	1
W	0	1	W
W	1	0	1
W	1	1	0
0	W	0	1
0	W	1	W
1	W	0	1
1	W	1	0
0	0	W	1
0	1	W	W
1	0	W	W
1	1	W	W

W	0	W	W
W	W	0	1
W	1	W	W
W	W	1	W
0	W	W	W
1	W	W	W

W	W	W	W

Figure 91 The Defective OAI21 Circuit “DOAI211”. The defect on the output, either resistive or open, gives an undetermined value for all input conditions.

Table 35 The Truth Table for the Defective OAI21 Circuit “DOAI211”.

A	B	C	Z
x	x	x	W

Figure 92 The Defective OAI21 Circuit “DOAI212”. The open defect affects input C.

Table 36 The Abbreviated Truth Table for the Defective OAI21 Circuit “DOAI212”

A	B	C	Z
0	0	0	1
0	0	1	1
0	1	0	A
0	1	1	V
1	0	0	A
1	0	1	V
1	1	0	A
1	1	1	V

0	0	W	1
W	x	x	W
x	W	x	W
1	x	W	W
x	1	W	W

Figure 93 The Defective OAI21 Circuit “DOAI213”. The open defect affects the pmos transistor tied to input C. This means that the output can not be pulled high under some input conditions. This can be seen in the truth table shown below.

Table 37 The Truth Table for the Defective OAI21 Circuit “DOAI213”

A	B	C	Z
0	0	0	1
0	0	1	1
0	1	0	A
0	1	1	0
1	0	0	A
1	0	1	0
1	1	0	A
1	1	1	0

W	0	0	W
W	0	1	W
W	1	0	A
W	1	1	0
0	W	0	A
0	W	1	W
1	W	0	A
1	W	1	0
0	0	W	1
0	1	W	W
1	0	W	W
1	1	W	W

W	0	W	W
W	W	0	A
W	1	W	W
W	W	1	W
0	W	W	W
1	W	W	W

W	W	W	W

Figure 94 The Defective OAI21 Circuit “DOAI214”. The open defect affects the nmos transistor tied to input C. This means that the output can not be pulled low under some input conditions. As before, this can be seen in the truth table shown below.

Table 38 The Truth Table for the Defective OAI21 Circuit “DOAI214”

A	B	C	Z
0	0	0	1
0	0	1	1
0	1	0	1
0	1	1	V
1	0	0	1
1	0	1	V
1	1	0	1
1	1	1	V

W	0	0	1
W	0	1	W
W	1	0	1
W	1	1	W
0	W	0	1
0	W	1	W
1	W	0	1
1	W	1	W
0	0	W	1
0	1	W	W
1	0	W	W
1	1	W	W

W	0	W	W
W	W	0	1
W	1	W	W
W	W	1	W
0	W	W	W
1	W	W	W

W	W	W	W

Figure 95 The Defective OAI21 Circuit “DOAI215”. The open defect affects both of the gates of the transistors tied to input A. This means that the output can not be pulled high or pulled low under some input conditions.

Table 39 The Truth Table for the Defective OAI21 Circuit “DOAI215”.

A	B	C	Z
0	0	0	1
0	0	1	A
0	1	0	1
0	1	1	0
1	0	0	1
1	0	1	V
1	1	0	1
1	1	1	0

W	0	0	1
W	0	1	W
W	1	0	1
W	1	1	0
0	W	0	1
0	W	1	W
1	W	0	1
1	W	1	V
0	0	W	W
0	1	W	W
1	0	W	W
1	1	W	W

W	0	W	W
W	W	0	1
W	1	W	W
W	W	1	W
0	W	W	W
1	W	W	W

W	W	W	W

Figure 96 The Defective OAI21 Circuit “DOAI216”. The open defect is located on the pmos transistor tied to input A. This means that the output can not be pulled high under some input conditions.

Table 40 The Truth Table for the Defective OAI21 Circuit “DOAI216”.

A	B	C	Z
0	0	0	1
0	0	1	A
0	1	0	1
0	1	1	0
1	0	0	1
1	0	1	0
1	1	0	1
1	1	1	0

W	0	0	1
W	0	1	W
W	1	0	1
W	1	1	0
0	W	0	1
0	W	1	W
1	W	0	1
1	W	1	0
0	0	W	A
0	1	W	W
1	0	W	W
1	1	W	W

W	0	W	W
W	W	0	1
W	1	W	W
W	W	1	W
0	W	W	W
1	W	W	W

W	W	W	W

Figure 97 The Defective OAI21 Circuit “DOAI217”. The open defect is located on the nmos transistor tied to input A. This means that the output can not be pulled low under some input conditions.

Table 41 The Truth Table for the Defective OAI21 Circuit “DOAI217”.

A	B	C	Z
0	0	0	1
0	0	1	1
0	1	0	1
0	1	1	0
1	0	0	1
1	0	1	V
1	1	0	1
1	1	1	0

W	0	0	1
W	0	1	W
W	1	0	1
W	1	1	0
0	W	0	1
0	W	1	W
1	W	0	1
1	W	1	V
0	0	W	1
0	1	W	W
1	0	W	W
1	1	W	W

W	0	W	W
W	W	0	1
W	1	W	W
W	W	1	W
0	W	W	W
1	W	W	W

W	W	W	W

APPENDIX B: MAPPER CAD ALGORITHM TEST SOFTWARE

This section documents the computer software used to check the library of gates in the Mapper CAD algorithm. This QuickBasic code is used to determine the output of both the defectvie and defect-free logic gates, so a full listing of the gates in the library is required. Depending on the type of the defect and its location, the code can be as simple as a single line. However, most defects require a several lines of code to discover the appropriate gate output. This test code must be able to function properly regardless of the number of undetermined inputs to the gate. The following lines of computer code are used in the test version of the Mapper CAD algorithm.

‘Mapper CAD algorithm TEST CODE

‘Scott Thomas UNC-Charlotte iDDT Testing 2004

'This program tests the logic function of the gates.

CLS 'clear the screen

'set the gate and the inputs

xx% = 1

'nodes$(xx%, 1) = "NAND" 'checked and works

'nodes$(xx%, 1) = "NOR" 'checked and works

'nodes$(xx%, 1) = "INV" 'checked and works

'nodes$(xx%, 1) = "DNOR1" 'checked and works

'nodes$(xx%, 1) = "DNOR2" 'checked and works

'nodes$(xx%, 1) = "DNOR3" 'checked and works

'nodes$(xx%, 1) = "DNAND1" 'checked and works

'nodes$(xx%, 1) = "DNAND2" 'checked and works

'nodes$(xx%, 1) = "DNAND3" 'checked and works

'nodes$(xx%, 1) = "DINV1" 'checked and works

'nodes$(xx%, 1) = "DINV2" 'checked and works

'nodes$(xx%, 1) = "DINV3" 'checked and works

'nodes$(xx%, 1) = "AOI21" 'checked and works

'nodes$(xx%, 1) = "DAOI211" 'checked and works

'nodes$(xx%, 1) = "DAOI212" 'checked and works

'nodes$(xx%, 1) = "DAOI213" 'checked and works

'nodes$(xx%, 1) = "DAOI214" 'checked and works

'nodes$(xx%, 1) = "DAOI215" 'checked and works

'nodes$(xx%, 1) = "DAOI216" 'checked and works

'nodes$(xx%, 1) = "DAOI217" 'checked and works

'nodes$(xx%, 1) = "OAI21" 'checked and works

'nodes$(xx%, 1) = "DOAI211" 'checked and works

'nodes$(xx%, 1) = "DOAI212" 'checked and works

'nodes$(xx%, 1) = "DOAI213" 'checked and works

'nodes$(xx%, 1) = "DOAI214" 'checked and works

'nodes$(xx%, 1) = "DOAI215" 'checked and works

'nodes$(xx%, 1) = "DOAI216" 'checked and works

'nodes$(xx%, 1) = "DOAI217" 'checked and works

'set the output node

nodes$(xx%, 2) = "output"

'set nuber of inputs

'ncount% = 4

ncount% = 3

'ncount% = 1

'tvar$(1) = "0"

'tvar$(1) = "W"

'tvar$(1) = "1"

tvar$(1) = "0": tvar$(2) = "0": tvar$(3) = "0"

'tvar$(1) = "0": tvar$(2) = "1": tvar$(3) = "1"

'tvar$(1) = "W": tvar$(2) = "1": tvar$(3) = "0"

'tvar$(1) = "0": tvar$(2) = "0": tvar$(3) = "W"

'tvar$(1) = "1": tvar$(2) = "W": tvar$(3) = "1"

'tvar$(1) = "1": tvar$(2) = "0": tvar$(3) = "0"

'tvar$(1) = "1": tvar$(2) = "0": tvar$(3) = "1"

'tvar$(1) = "1": tvar$(2) = "1": tvar$(3) = "1"

'tvar$(1) = "W": tvar$(2) = "W": tvar$(3) = "0"

'tvar$(1) = "W": tvar$(2) = "W": tvar$(3) = "W"

'tvar$(1) = "0": tvar$(2) = "0": tvar$(3) = "0": tvar$(4) = "0"

'tvar$(1) = "1": tvar$(2) = "0": tvar$(3) = "0": tvar$(4) = "0"

'tvar$(1) = "0": tvar$(2) = "1": tvar$(3) = "1": tvar$(4) = "1"

'tvar$(1) = "0": tvar$(2) = "0": tvar$(3) = "0": tvar$(4) = "1"

'tvar$(1) = "0": tvar$(2) = "0": tvar$(3) = "0": tvar$(4) = "W"

'tvar$(1) = "0": tvar$(2) = "1": tvar$(3) = "1": tvar$(4) = "W"

'tvar$(1) = "1": tvar$(2) = "1": tvar$(3) = "1": tvar$(4) = "W"

'tvar$(1) = "1": tvar$(2) = "1": tvar$(3) = "1": tvar$(4) = "1"

'tvar$(1) = "W": tvar$(2) = "1": tvar$(3) = "1": tvar$(4) = "1"

'tvar$(1) = "W": tvar$(2) = "W": tvar$(3) = "W": tvar$(4) = "W"

PRINT "INPUTS:"

FOR zzz% = 1 TO ncount%

PRINT tvar$(zzz%); " ";

NEXT zzz%

'Next find if all 0's or all 1's.

nofzero% = 0 'clear the number of zeroes

nofones% = 0 'clear the number of ones

varpres% = 0 'clear the variable present flag

allzero% = 0 'clear the all zero flag

allones% = 0 'clear the all ones flag

firstin% = 2 'set the first variable default

nvari% = 0 'clear the nubmer of variable inputs

'Change the value of the first variable if it's one

IF tvar$(1) = "0" THEN firstin% = 0

IF tvar$(1) = "1" THEN firstin% = 1

FOR zz% = 1 TO ncount%

IF tvar$(zz%) = "0" THEN nofzero% = nofzero% + 1

IF tvar$(zz%) = "1" THEN nofones% = nofones% + 1

IF tvar$(zz%) <> "0" AND tvar$(zz%) <> "1" THEN nvari% = nvari% + 1

NEXT zz%

'This finds an undetermined variable on the inputs

IF nvari% > 0 THEN varpres% = 1

'This determines if the inputs are all one level

IF nofzero% = ncount% THEN allzero% = 1

IF nofones% = ncount% THEN allones% = 1

'check

PRINT "nofzero is ", nofzero%

PRINT "nofones is ", nofones%

PRINT "varpres is ", varpres%

PRINT "allzero is ", allzero%

PRINT "allones is ", allones%

PRINT "firstin is ", firstin%

PRINT "nvari is ", nvari%

'Make the logical assignment. FULL LISTING HERE

IF nodes$(xx%, 1) = "NAND" THEN

IF varpres% = 0 THEN 'variable not present

IF allones% = 1 THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

IF nofzero% > 0 THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

END IF'variable not present

IF varpres% = 1 THEN 'variable present

IF nofzero% = 0 THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

IF nofzero% > 0 THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

END IF'variable present

END IF '---------"NAND"

IF nodes$(xx%, 1) = "NOR" THEN

IF allzero% = 1 THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

IF nofones% > 0 THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

IF varpres% = 1 AND nofones% = 0 THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

END IF '----------"NOR"

IF nodes$(xx%, 1) = "INV" THEN

IF allzero% = 1 THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

IF allones% = 1 THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

IF varpres% = 1 THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

END IF '----------"INV"

IF nodes$(xx%, 1) = "DNOR1" THEN

'a resistive or open defect on the input or output

nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

END IF '----------"DNOR1"

IF nodes$(xx%, 1) = "DNOR2" THEN

'an open defect on one of the pmos transistors

IF allzero% = 1 THEN nodes$(xx%, 2) = "A-" + nodes$(xx%, 2)

IF nofones% > 0 THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

IF varpres% = 1 AND nofones% = 0 THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

END IF '----------"DNOR2"

IF nodes$(xx%, 1) = "DNOR3" THEN

'an open defect on one of the nmos transistors

IF varpres% = 0 THEN 'variable not present

IF allzero% = 1 THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

IF firstin% = 1 AND nofones% = 1 THEN nodes$(xx%, 2) = "V-" + nodes$(xx%, 2)

IF firstin% = 1 AND nofones% > 1 THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

IF firstin% = 0 AND nofones% > 0 THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

END IF 'variable not present

IF varpres% = 1 THEN 'variable present

IF firstin% = 2 AND nofones% > 0 THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

IF firstin% = 2 AND nofones% = 0 THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

IF firstin% = 0 AND nofones% > 0 THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

IF firstin% = 0 AND nofones% = 0 THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

IF firstin% = 1 AND nofones% > 1 THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

IF firstin% = 1 AND nofones% = 1 THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

END IF 'variable present

END IF '----------"DNOR3"

IF nodes$(xx%, 1) = "DNAND1" THEN

'a resistive or open defect on the input or output

nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

END IF '---------"DNAND1"

IF nodes$(xx%, 1) = "DNAND2" THEN

'an open defect on one of the pmos transistors

IF varpres% = 0 THEN

IF allones% = 1 THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

IF firstin% = 0 AND nofones% + 1 = ncount% THEN nodes$(xx%, 2) = "A-" + nodes$(xx%, 2)

IF firstin% = 0 AND nofzero% > 1 THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

IF firstin% = 1 AND nofzero% > 0 THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

END IF'variable not present

IF varpres% = 1 THEN

IF firstin% = 2 AND nofzero% > 0 THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

IF firstin% = 2 AND nofones% + 1 = ncount% THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

IF firstin% = 2 AND nofzero% = 0 THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

IF firstin% = 1 AND nofzero% > 0 THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

IF firstin% = 1 AND nofzero% = 0 THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

IF firstin% = 0 AND nofzero% = 1 THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

IF firstin% = 0 AND nofzero% > 1 THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

END IF'variable present

END IF '---------"DNAND2"

IF nodes$(xx%, 1) = "DNAND3" THEN

'open on one of the nmos transistors

IF varpres% = 0 THEN

IF nofzero% > 0 THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

IF nofones% = ncount% THEN nodes$(xx%, 2) = "V-" + nodes$(xx%, 2)

END IF 'variable not present

IF varpres% = 1 THEN

IF firstin% > 0 AND nofzero% > 0 THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

IF firstin% > 0 AND nofzero% = 0 THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

IF firstin% = 0 THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

END IF 'variable present

END IF '------------"DNAND3"

IF nodes$(xx%, 1) = "DINV1" THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

IF nodes$(xx%, 1) = "DINV2" THEN

IF allzero% = 1 THEN nodes$(xx%, 2) = "A-" + nodes$(xx%, 2)

IF allones% = 1 THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

IF varpres% = 1 THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

END IF '------------"DINV2"

IF nodes$(xx%, 1) = "DINV3" THEN

IF allzero% = 1 THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

IF allones% = 1 THEN nodes$(xx%, 2) = "V-" + nodes$(xx%, 2)

IF varpres% = 1 THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

END IF '------------"DINV3"

IF nodes$(xx%, 1) = "AOI21" THEN

IF nvari% = 0 THEN

IF (tvar$(1) = "0" OR tvar$(2) = "0") AND tvar$(3) = "0" THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

IF (tvar$(1) = "0" OR tvar$(2) = "0") AND tvar$(3) = "1" THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

IF (tvar$(1) = "1" AND tvar$(2) = "1") THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

END IF 'nvari is zero

IF nvari% = 1 THEN

'the first variable is undetermined

IF (tvar$(1) <> "1" AND tvar$(1) <> "0") AND tvar$(3) = "1" THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

IF (tvar$(1) <> "1" AND tvar$(1) <> "0") AND tvar$(2) = "0" AND tvar$(3) = "0" THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

IF (tvar$(1) <> "1" AND tvar$(1) <> "0") AND tvar$(2) = "1" AND tvar$(3) = "0" THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

'the second variable is undetermined

IF (tvar$(2) <> "1" AND tvar$(2) <> "0") AND tvar$(1) = "0" AND tvar$(3) = "0" THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

IF (tvar$(2) <> "1" AND tvar$(2) <> "0") AND tvar$(3) = "1" THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

IF (tvar$(2) <> "1" AND tvar$(2) <> "0") AND tvar$(1) = "1" AND tvar$(3) = "0" THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

'the third variable is undetermined

IF (tvar$(3) <> "1" AND tvar$(3) <> "0") AND tvar$(1) = "1" AND tvar$(2) = "1" THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

IF (tvar$(3) <> "1" AND tvar$(3) <> "0") AND (tvar$(1) = "0" OR tvar$(2) = "0") THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

END IF'nvari is one

IF nvari% > 1 THEN

IF tvar$(3) = "1" THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

IF tvar$(3) <> "1" THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

END IF'nvari two or three

END IF'-------------"AOI21"

IF nodes$(xx%, 1) = "DAOI211" THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

IF nodes$(xx%, 1) = "DAOI212" THEN

IF tvar$(1) = "1" AND tvar$(2) = "1" THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

IF (tvar$(1) <> "1" OR tvar$(2) <> "1") THEN nodes$(xx%, 2) = "W-" + nodes$(xx%,2)

END IF'-------------"DAOI212"

IF nodes$(xx%, 1) = "DAOI213" THEN

IF nvari% = 0 THEN

IF (tvar$(1) = "0" OR tvar$(2) = "0") AND tvar$(3) = "0" THEN nodes$(xx%, 2) = "A-" + nodes$(xx%, 2)

IF (tvar$(1) = "1" AND tvar$(2) = "1") OR tvar$(3) = "1" THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

END IF'nvari is zero

IF nvari% = 1 THEN

'first variable is undetermined

IF (tvar$(1) <> "1" AND tvar$(1) <> "0") AND tvar$(3) = "0" THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

IF (tvar$(1) <> "1" AND tvar$(1) <> "0") AND tvar$(3) = "1" THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

'second variable is undetermined

IF (tvar$(2) <> "1" AND tvar$(2) <> "0") AND tvar$(3) = "0" THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

IF (tvar$(2) <> "1" AND tvar$(2) <> "0") AND tvar$(3) = "1" THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

'third variable is undetermined

IF (tvar$(3) <> "1" AND tvar$(3) <> "0") AND tvar$(1) = "1" AND tvar$(2) = "1" THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

IF (tvar$(3) <> "1" AND tvar$(3) <> "0") AND (tvar$(1) = "0" OR tvar$(2) = "0") THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

END IF'nvari is one

IF nvari% > 1 THEN

IF tvar$(3) = "1" THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

IF tvar$(3) <> "1" THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

END IF'nvari is two or three

END IF'-------------"DAOI213"

IF nodes$(xx%, 1) = "DAOI214" THEN

IF nvari% = 0 THEN

IF (tvar$(1) = "0" OR tvar$(2) = "0") AND tvar$(3) = "0" THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

IF (tvar$(1) = "0" OR tvar$(2) = "0") AND tvar$(3) = "1" THEN nodes$(xx%, 2) = "V-" + nodes$(xx%, 2)

IF (tvar$(1) = "1" AND tvar$(2) = "1") THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

END IF'nvari is zero

IF nvari% = 1 THEN

'first variable is undetermined

IF (tvar$(1) <> "0" AND tvar$(1) <> "1") AND tvar$(3) = "1" THEN nodes$(xx%, 2) = "V-" + nodes$(xx%, 2)

IF (tvar$(1) <> "0" AND tvar$(1) <> "1") AND tvar$(2) = "0" AND tvar$(3) = "0" THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

IF (tvar$(1) <> "0" AND tvar$(1) <> "1") AND tvar$(2) = "1" AND tvar$(3) = "0" THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

'second variable is undetermined

IF (tvar$(2) <> "0" AND tvar$(2) <> "1") AND tvar$(1) = "0" AND tvar$(3) = "0" THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

IF (tvar$(2) <> "0" AND tvar$(2) <> "1") AND tvar$(1) = "0" AND tvar$(3) = "1" THEN nodes$(xx%, 2) = "V-" + nodes$(xx%, 2)

IF (tvar$(2) <> "0" AND tvar$(2) <> "1") AND tvar$(1) = "1" THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

'third variable is undetermined

IF (tvar$(3) <> "0" AND tvar$(3) <> "1") AND tvar$(1) = "1" AND tvar$(2) = "1" THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

IF (tvar$(3) <> "0" AND tvar$(3) <> "1") AND (tvar$(1) = "0" OR tvar$(2) = "0") THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

END IF'nvari is one

IF nvari% > 1 THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

END IF'-------------"DAOI214"

IF nodes$(xx%, 1) = "DAOI215" THEN

IF nvari% = 0 THEN

IF tvar$(3) = "0" THEN

IF tvar$(2) = "0" THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

IF tvar$(2) = "1" THEN

IF tvar$(1) = "0" THEN nodes$(xx%, 2) = "A-" + nodes$(xx%, 2)

IF tvar$(1) = "1" THEN nodes$(xx%, 2) = "V-" + nodes$(xx%, 2)

END IF'tvar 2 is one

END IF 'tvar 3 is zero

IF tvar$(3) = "1" THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

END IF'nvari is zero

IF nvari% = 1 THEN

'first variable is undetermined

IF (tvar$(1) <> "0" AND tvar$(1) <> "1") THEN

IF tvar$(3) = "0" THEN

IF tvar$(2) = "0" THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

IF tvar$(2) = "1" THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

END IF'c is zero

IF tvar$(3) = "1" THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

END IF'a is undetermined

'second variable is undetermined

IF (tvar$(2) <> "0" AND tvar$(2) <> "1") THEN

IF tvar$(3) = "0" THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

IF tvar$(3) = "1" THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

END IF'b is undetermined

IF (tvar$(3) <> "0" AND tvar$(3) <> "1") THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

END IF'nvari is one

IF nvari% > 1 THEN

IF tvar$(3) = "1" THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

IF tvar$(3) <> "1" THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

END IF'nvari is greater than one

END IF'-------------"DAOI215"

IF nodes$(xx%, 1) = "DAOI216" THEN

IF nvari% = 0 THEN

IF tvar$(2) = "0" AND tvar$(3) = "0" THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

IF tvar$(1) = "0" AND tvar$(2) = "1" AND tvar$(3) = "0" THEN nodes$(xx%, 2) = "A-" + nodes$(xx%, 2)

IF tvar$(1) = "0" AND tvar$(3) = "1" THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

IF tvar$(1) = "1" AND (tvar$(2) = "1" OR tvar$(3) = "1") THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

END IF'nvari is zero

IF nvari% = 1 THEN

IF (tvar$(1) <> "0" AND tvar$(1) <> "1") THEN

IF tvar$(2) = "0" AND tvar$(3) = "0" THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

IF tvar$(2) = "1" AND tvar$(3) = "0" THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

IF tvar$(3) = "1" THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

END IF'a is undetermined

IF (tvar$(2) <> "0" AND tvar$(2) <> "1") THEN

IF tvar$(3) = "0" THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

IF tvar$(3) = "1" THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

END IF'b is undetermined

IF (tvar$(3) <> "0" AND tvar$(3) <> "1") THEN

IF (tvar$(1) = "1" AND tvar$(2) = "1") THEN nodes$(xx%, 2) = "0-" + nodes$(xx%,2)

IF (tvar$(1) = "0" OR tvar$(2) = "0") THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

END IF'c is undetermined

END IF'nvari is one

IF nvari% > 1 THEN

IF tvar$(3) = "1" THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

IF tvar$(3) <> "1" THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

END IF'nvari is greater than one

END IF'-------------"DAOI216"

IF nodes$(xx%, 1) = "DAOI217" THEN

IF nvari% = 0 THEN

IF tvar$(1) = "0" THEN

IF tvar$(3) = "0" THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

IF tvar$(3) = "1" THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

END IF'a is zero

IF tvar$(1) = "1" THEN

IF tvar$(3) = "1" THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

IF tvar$(2) = "0" AND tvar$(3) = "0" THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

IF tvar$(2) = "1" AND tvar$(3) = "0" THEN nodes$(xx%, 2) = "V-" + nodes$(xx%, 2)

END IF'a is one

END IF'nvari is zero

IF nvari% = 1 THEN

IF (tvar$(1) <> "1" AND tvar$(1) <> "0") THEN

IF tvar$(2) = "0" AND tvar$(3) = "0" THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

IF tvar$(2) = "1" AND tvar$(3) = "0" THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

IF tvar$(3) = "1" THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

END IF'a is undetermined

IF (tvar$(2) <> "1" AND tvar$(2) <> "0") THEN

IF tvar$(1) = "0" AND tvar$(3) = "0" THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

IF tvar$(1) = "1" AND tvar$(3) = "0" THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

IF tvar$(3) = "1" THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

END IF'b is undetermined

IF (tvar$(3) <> "1" AND tvar$(3) <> "0") THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

END IF'nvari is one

IF nvari% > 1 THEN

IF tvar$(3) = "1" THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

IF tvar$(3) <> "1" THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

END IF'nvari is one or two

END IF'-------------"DAOI217"

IF nodes$(xx%, 1) = "OAI21" THEN

IF nvari% = 0 THEN

IF tvar$(1) = "0" THEN

IF tvar$(2) = "1" AND tvar$(3) = "1" THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

IF tvar$(2) = "0" OR tvar$(3) = "0" THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

END IF'a is zero

IF tvar$(1) = "1" THEN

IF tvar$(3) = "0" THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

IF tvar$(3) = "1" THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

END IF'a is one

END IF'nvari is zero

IF nvari% = 1 THEN

IF (tvar$(1) <> "0" AND tvar$(1) <> "1") THEN

IF tvar$(2) = "0" AND tvar$(3) = "1" THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

IF tvar$(2) = "1" AND tvar$(3) = "1" THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

IF tvar$(3) = "0" THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

END IF'a is undetermined

IF (tvar$(2) <> "0" AND tvar$(2) <> "1") THEN

IF tvar$(1) = "0" AND tvar$(3) = "1" THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

IF tvar$(1) = "1" AND tvar$(3) = "1" THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

IF tvar$(3) = "0" THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

END IF'b is undetermined

IF (tvar$(3) <> "0" AND tvar$(3) <> "1") THEN

IF (tvar$(1) = "0" AND tvar$(2) = "0") THEN nodes$(xx%, 2) = "1-" + nodes$(xx%,2)

IF (tvar$(1) = "1" OR tvar$(2) = "1") THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

END IF'c is undetermined

END IF'nvari is one

IF nvari% > 1 THEN

IF tvar$(3) = "0" THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

IF tvar$(3) <> "0" THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

END IF'nvari is greater than one

END IF'----------"OAI21"

IF nodes$(xx%, 1) = "DOAI211" THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

IF nodes$(xx%, 1) = "DOAI212" THEN

IF nvari% = 0 THEN

IF (tvar$(1) = "0" AND tvar$(2) = "0") THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

IF (tvar$(1) = "1" OR tvar$(2) = "1") THEN

IF tvar$(3) = "0" THEN nodes$(xx%, 2) = "A-" + nodes$(xx%, 2)

IF tvar$(3) = "1" THEN nodes$(xx%, 2) = "V-" + nodes$(xx%, 2)

END IF'a is one or b is one

END IF'nvari is zero

IF nvari% > 0 THEN

IF (tvar$(1) = "0" AND tvar$(2) = "0") THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

IF (tvar$(1) <> "0" OR tvar$(2) <> "0") THEN nodes$(xx%, 2) = "W-" + nodes$(xx%,2)

END IF'nvari is one or more

END IF'-------------"DOAI212"

IF nodes$(xx%, 1) = "DOAI213" THEN

IF nvari% = 0 THEN

IF (tvar$(1) = "0" AND tvar$(2) = "0") THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

IF (tvar$(1) = "1" OR tvar$(2) = "1") THEN

IF tvar$(3) = "0" THEN nodes$(xx%, 2) = "A-" + nodes$(xx%, 2)

IF tvar$(3) = "1" THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

END IF'a is one or b is one

END IF'nvari is zero

IF nvari% = 1 THEN

IF (tvar$(1) <> "0" AND tvar$(1) <> "1") THEN

IF tvar$(2) = "1" AND tvar$(3) = "0" THEN nodes$(xx%, 2) = "A-" + nodes$(xx%, 2)

IF tvar$(2) = "1" AND tvar$(3) = "1" THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

IF tvar$(2) = "0" THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

END IF'a is undetermined

IF (tvar$(2) <> "0" AND tvar$(2) <> "1") THEN

IF tvar$(1) = "0" AND tvar$(3) = "1" THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

IF tvar$(1) = "1" AND tvar$(3) = "1" THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

IF tvar$(3) = "0" THEN nodes$(xx%, 2) = "A-" + nodes$(xx%, 2)

END IF'b is undetermined

IF (tvar$(3) <> "0" AND tvar$(3) <> "1") THEN

IF tvar$(1) = "0" AND tvar$(2) = "0" THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

IF tvar$(1) = "1" OR tvar$(2) = "1" THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

END IF'c is undetermined

END IF'nvari is one

IF nvari% > 1 THEN

IF tvar$(3) = "0" THEN nodes$(xx%, 2) = "A-" + nodes$(xx%, 2)

IF tvar$(3) <> "0" THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

END IF'nvari is greater than one

END IF'-------------"DOAI213"

IF nodes$(xx%, 1) = "DOAI214" THEN

IF nvari% = 0 THEN

IF (tvar$(1) = "0" AND tvar$(2) = "0") THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

IF (tvar$(1) = "1" OR tvar$(2) = "1") THEN

IF tvar$(3) = "0" THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

IF tvar$(3) = "1" THEN nodes$(xx%, 2) = "V-" + nodes$(xx%, 2)

END IF'a is one or b is one

END IF'nvari is zero

IF nvari% = 1 THEN

IF (tvar$(1) <> "0" AND tvar$(1) <> "1") OR (tvar$(2) <> "0" AND tvar$(2) <> "1") THEN

IF tvar$(3) = "0" THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

IF tvar$(3) = "1" THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

END IF'if a or b is undetermined

IF (tvar$(3) <> "0" AND tvar$(3) <> "1") THEN

IF (tvar$(1) = "0" AND tvar$(2) = "0") THEN nodes$(xx%, 2) = "1-" + nodes$(xx%,2)

IF (tvar$(1) = "1" OR tvar$(2) = "1") THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

END IF'c is undetermined

END IF'nvari is one

IF nvari% > 1 THEN

IF tvar$(3) = "0" THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

IF tvar$(3) <> "0" THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

END IF'nvari is greater than one

END IF'-------------"DOAI214"

IF nodes$(xx%, 1) = "DOAI215" THEN

IF nvari% = 0 THEN

IF tvar$(1) = "0" THEN

IF tvar$(3) = "1" THEN

IF tvar$(2) = "0" THEN nodes$(xx%, 2) = "A-" + nodes$(xx%, 2)

IF tvar$(2) = "1" THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

END IF'c is one

IF tvar$(3) = "0" THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

END IF'a is zero

IF tvar$(1) = "1" THEN

IF tvar$(3) = "1" THEN

IF tvar$(2) = "0" THEN nodes$(xx%, 2) = "V-" + nodes$(xx%, 2)

IF tvar$(2) = "1" THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

END IF'c is one

IF tvar$(3) = "0" THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

END IF'a is one

END IF'nvari is zero

IF nvari% = 1 THEN

IF (tvar$(1) <> "0" AND tvar$(1) <> "1") THEN

IF tvar$(2) = "0" AND tvar$(3) = "1" THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

IF tvar$(2) = "1" AND tvar$(3) = "1" THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

IF tvar$(3) = "0" THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

END IF'a is undetermined

IF (tvar$(2) <> "0" AND tvar$(2) <> "1") THEN

IF tvar$(1) = "0" AND tvar$(3) = "1" THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

IF tvar$(1) = "1" AND tvar$(3) = "1" THEN nodes$(xx%, 2) = "V-" + nodes$(xx%, 2)

IF tvar$(3) = "0" THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

END IF'b is undetermined

IF tvar$(3) <> "0" AND tvar$(3) <> "1" THEN nodes$(xx%, 2) = "W-" + nodes$(xx%,2)

END IF'nvari is one

IF nvari% > 1 THEN

IF tvar$(3) = "0" THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

IF tvar$(3) <> "0" THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

END IF'nvari is greater than one

END IF'-------------"DOAI215"

IF nodes$(xx%, 1) = "DOAI216" THEN

IF nvari% = 0 THEN

IF tvar$(1) = "0" THEN

IF tvar$(3) = "1" THEN

IF tvar$(2) = "0" THEN nodes$(xx%, 2) = "A-" + nodes$(xx%, 2)

IF tvar$(2) = "1" THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

END IF'c is one

IF tvar$(3) = "0" THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

END IF'a is zero

IF tvar$(1) = "1" THEN

IF tvar$(3) = "0" THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

IF tvar$(3) = "1" THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

END IF'a is one

END IF'nvari is zero

IF nvari% = 1 THEN

IF (tvar$(1) <> "0" AND tvar$(1) <> "1") THEN

IF tvar$(3) = "1" THEN

IF tvar$(2) = "0" THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

IF tvar$(2) = "1" THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

END IF'c is one

IF tvar$(3) = "0" THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

END IF'a is undetermined

IF (tvar$(2) <> "0" AND tvar$(2) <> "1") THEN

IF tvar$(3) = "1" THEN

IF tvar$(1) = "0" THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

IF tvar$(1) = "1" THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

END IF'c is one

IF tvar$(3) = "0" THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

END IF'b is undetermined

IF (tvar$(3) <> "0" AND tvar$(3) <> "1") THEN

IF tvar$(1) = "0" AND tvar$(2) = "0" THEN nodes$(xx%, 2) = "A-" + nodes$(xx%, 2)

IF tvar$(1) = "1" OR tvar$(2) = "1" THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

END IF'c is undetermined

END IF'nvari is one

IF nvari% > 1 THEN

IF tvar$(3) = "0" THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

IF tvar$(3) <> "0" THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

END IF'nvari is greater than one

END IF'-------------"DOAI216"

IF nodes$(xx%, 1) = "DOAI217" THEN

IF nvari% = 0 THEN

IF tvar$(1) = "0" THEN

IF tvar$(2) = "1" AND tvar$(3) = "1" THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

IF tvar$(2) = "0" OR tvar$(3) = "0" THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

END IF'a is zero

IF tvar$(1) = "1" THEN

IF tvar$(3) = "1" THEN

IF tvar$(2) = "0" THEN nodes$(xx%, 2) = "V-" + nodes$(xx%, 2)

IF tvar$(2) = "1" THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

END IF'c is one

IF tvar$(3) = "0" THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

END IF'a is one

END IF'nvari is zero

IF nvari% = 1 THEN

IF (tvar$(1) <> "0" AND tvar$(1) <> "1") THEN

IF tvar$(3) = "1" THEN

IF tvar$(2) = "0" THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

IF tvar$(2) = "1" THEN nodes$(xx%, 2) = "0-" + nodes$(xx%, 2)

END IF'c is one

IF tvar$(3) = "0" THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

END IF'a is undetermined

IF (tvar$(2) <> "0" AND tvar$(2) <> "1") THEN

IF tvar$(3) = "1" THEN

IF tvar$(1) = "0" THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

IF tvar$(1) = "1" THEN nodes$(xx%, 2) = "V-" + nodes$(xx%, 2)

END IF'c is one

IF tvar$(3) = "0" THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

END IF'b is undetermined

IF (tvar$(3) <> "0" AND tvar$(3) <> "1") THEN

IF tvar$(1) = "0" AND tvar$(2) = "0" THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

IF tvar$(1) = "1" OR tvar$(2) = "1" THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

END IF'c is undetermined

END IF'nvari equals one

IF nvari% > 1 THEN

IF tvar$(3) = "0" THEN nodes$(xx%, 2) = "1-" + nodes$(xx%, 2)

IF tvar$(3) <> "0" THEN nodes$(xx%, 2) = "W-" + nodes$(xx%, 2)

END IF'nvari is greater than one

END IF'-------------"DOAI217"

'Check the node entry

PRINT "nodes xx 1 is... ", nodes$(xx%, 1)

PRINT "nodes xx 2 is... ", nodes$(xx%, 2)

'INPUT "press enter", wait$

‘END of Mapper CAD algorithm TEST CODE

END

APPENDIX C: SPICE FILE SAMPLE

Before the layout of an IC can be converted into a Spice file for the purpose of running computer simulations, some preliminary steps must be taken. All of the important nodes must be labeled. Adding this label allows the user to differentiate these nodes from the other “anonymous” nodes tagged with indescript numbers. Inputs and outputs must be labeled, as well as important internal nodes such as the defect location.

After the file has been converted to an intermediate Spice file, additional information must be added to the file. Information such as the driving inputs, the voltage supplies, and the transistor data are necessary to instruct the simulator on what actions to execute. The following lines of Spice code provide a sample of the additional information added to the simulation files.

*Additional library files:

.include polyres.lib
.include npdat.lib
.include package_40_2.cir

***Spice file created from layout***

*Information used at the defect location:
*Rdefect defside1 defside2 1ohm
*Cdefect defside1 defside2 0.01F
*Cdefect2 defside1 0 1F

*Power supplies and package information follows:

Vforpf ppin12 0 5V
xpin12 pfpow ppin12 p9_12_29_32
Vconn pfpow VDD 0V

xpincarry carry ppin11 p10_11_30_31
Ccarry ppin11 0 1fF

xaoutput addout ppin10 p10_11_30_31
Caout ppin10 0 1fF

Vgnd Gnd 0 0V
Vcon1 ppins 0 0V
xpfg pfgnd ppins p6_15_26_35
xcgn cktgnd ppins p10_11_30_31

Riddt ppin07 newcktpow 1k
xcpower cktpow ppin07 p7_14_27_34
Vckt newcktpow 0 5V

Rprobe ppin07 0 20k
Cprobe ppin07 0 0.5pF

vinpB ppin09 0 0V
xinBB Bin ppin09 p9_12_29_32

vinpA ppin08 0 pwl (0 0, 96ns 0V, 100ns 5V, 196ns 5V, 200ns 0V)
xinAA Ain ppin08 p8_13_28_33

*Time and step information for simulations:

.tran 0.1ns 300ns

*Nodes shown for output information:

.plot V(Ain)
.plot I(Riddt)
.plot V(Addout) V(carry)

*** the end ***

A	B	C	D	Z
0	0	0	0	1
0	0	0	1	1
0	0	1	0	1
0	0	1	1	1
0	1	0	0	1
0	1	0	1	1
0	1	1	0	1
0	1	1	1	1
1	0	0	0	1
1	0	0	1	1
1	0	1	0	1
1	0	1	1	1
1	1	0	0	1
1	1	0	1	1
1	1	1	0	1
1	1	1	1	0
W	0	x	x	1
W	1	1	1	W

A	B	C	D	Z
0	0	0	0	1
0	0	0	1	1
0	0	1	0	1
0	0	1	1	1
0	1	0	0	1
0	1	0	1	1
0	1	1	0	1
0	1	1	1	A
1	0	0	0	1
1	0	0	1	1
1	0	1	0	1
1	0	1	1	1
1	1	0	0	1
1	1	0	1	1
1	1	1	0	1
1	1	1	1	0
x	W	0	x	1
x	W	1	1	W

A	B	C	D	Z
0	0	0	0	1
0	0	0	1	1
0	0	1	0	1
0	0	1	1	1
0	1	0	0	1
0	1	0	1	1
0	1	1	0	1
0	1	1	1	1
1	0	0	0	1
1	0	0	1	1
1	0	1	0	1
1	0	1	1	1
1	1	0	0	1
1	1	0	1	1
1	1	1	0	1
1	1	1	1	V
0	W	x	x	1
x	W	1	1	W

A	B	C	Z
W	0	0	1
W	0	1	0
W	1	0	W
W	1	1	0
0	W	0	1
0	W	1	0
1	W	0	W
1	W	1	0
0	0	W	W
0	1	W	W
1	0	W	W
1	1	W	0

W	0	W	W
W	W	0	W
W	1	W	W
W	W	1	0
0	W	W	W
1	W	W	W

W	W	W	W

A	B	C	Z
0	0	0	W
0	0	1	W
0	1	0	W
0	1	1	W
1	0	0	W
1	0	1	W
1	1	0	0
1	1	1	0

W	0	0	W
W	0	1	W
W	1	0	W
W	1	1	W
0	W	0	W
0	W	1	W
1	W	0	W
1	W	1	W
0	0	W	W
0	1	W	W
1	0	W	W
1	1	W	0

W	0	W	W
W	W	0	W
W	1	W	W
W	W	1	W
0	W	W	W
1	W	W	W

W	W	W	W

A	B	C	Z
0	0	0	A
0	0	1	0
0	1	0	A
0	1	1	0
1	0	0	A
1	0	1	0
1	1	0	0
1	1	1	0

W	0	0	W
W	0	1	0
W	1	0	W
W	1	1	0
0	W	0	W
0	W	1	0
1	W	0	W
1	W	1	0
0	0	W	W
0	1	W	W
1	0	W	W
1	1	W	0

W	0	W	W
W	W	0	W
W	1	W	W
W	W	1	0
0	W	W	W
1	W	W	W

W	W	W	W

A	B	C	Z
0	0	0	1
0	0	1	V
0	1	0	1
0	1	1	V
1	0	0	1
1	0	1	V
1	1	0	0
1	1	1	0

W	0	0	1
W	0	1	V
W	1	0	W
W	1	1	V
0	W	0	1
0	W	1	V
1	W	0	W
1	W	1	W
0	0	W	W
0	1	W	W
1	0	W	W
1	1	W	0

W	0	W	W
W	W	0	W
W	1	W	W
W	W	1	W
0	W	W	W
1	W	W	W

W	W	W	W

A	B	C	Z
0	0	0	1
0	0	1	0
0	1	0	A
0	1	1	0
1	0	0	1
1	0	1	0
1	1	0	V
1	1	1	0

W	0	0	1
W	0	1	0
W	1	0	W
W	1	1	0
0	W	0	W
0	W	1	0
1	W	0	W
1	W	1	0
0	0	W	W
0	1	W	W
1	0	W	W
1	1	W	W

W	0	W	W
W	W	0	W
W	1	W	W
W	W	1	0
0	W	W	W
1	W	W	W

W	W	W	W

A	B	C	Z
0	0	0	1
0	0	1	0
0	1	0	A
0	1	1	0
1	0	0	1
1	0	1	0
1	1	0	0
1	1	1	0

W	0	0	1
W	0	1	0
W	1	0	W
W	1	1	0
0	W	0	W
0	W	1	0
1	W	0	W
1	W	1	0
0	0	W	W
0	1	W	W
1	0	W	W
1	1	W	0

W	0	W	W
W	W	0	W
W	1	W	W
W	W	1	0
0	W	W	W
1	W	W	W

W	W	W	W

A	B	C	Z
0	0	0	1
0	0	1	0
0	1	0	1
0	1	1	0
1	0	0	1
1	0	1	0
1	1	0	V
1	1	1	0

W	0	0	1
W	0	1	0
W	1	0	W
W	1	1	0
0	W	0	1
0	W	1	0
1	W	0	W
1	W	1	0
0	0	W	W
0	1	W	W
1	0	W	W
1	1	W	W

W	0	W	W
W	W	0	W
W	1	W	W
W	W	1	0
0	W	W	W
1	W	W	W

W	W	W	W

A	B	C	D	Z
0	0	0	0	1
0	0	0	1	1
0	0	1	0	1
0	0	1	1	1
0	1	0	0	1
0	1	0	1	1
0	1	1	0	1
0	1	1	1	1
1	0	0	0	1
1	0	0	1	1
1	0	1	0	1
1	0	1	1	1
1	1	0	0	1
1	1	0	1	1
1	1	1	0	1
1	1	1	1	0
W	0	x	x	1
W	1	1	1	W

A	B	C	D	Z
0	0	0	0	1
0	0	0	1	1
0	0	1	0	1
0	0	1	1	1
0	1	0	0	1
0	1	0	1	1
0	1	1	0	1
0	1	1	1	A
1	0	0	0	1
1	0	0	1	1
1	0	1	0	1
1	0	1	1	1
1	1	0	0	1
1	1	0	1	1
1	1	1	0	1
1	1	1	1	0
x	W	0	x	1
x	W	1	1	W

A	B	C	D	Z
0	0	0	0	1
0	0	0	1	1
0	0	1	0	1
0	0	1	1	1
0	1	0	0	1
0	1	0	1	1
0	1	1	0	1
0	1	1	1	1
1	0	0	0	1
1	0	0	1	1
1	0	1	0	1
1	0	1	1	1
1	1	0	0	1
1	1	0	1	1
1	1	1	0	1
1	1	1	1	V
0	W	x	x	1
x	W	1	1	W

A	B	C	Z
W	0	0	1
W	0	1	0
W	1	0	W
W	1	1	0
0	W	0	1
0	W	1	0
1	W	0	W
1	W	1	0
0	0	W	W
0	1	W	W
1	0	W	W
1	1	W	0

W	0	W	W
W	W	0	W
W	1	W	W
W	W	1	0
0	W	W	W
1	W	W	W

W	W	W	W

A	B	C	Z
0	0	0	W
0	0	1	W
0	1	0	W
0	1	1	W
1	0	0	W
1	0	1	W
1	1	0	0
1	1	1	0

W	0	0	W
W	0	1	W
W	1	0	W
W	1	1	W
0	W	0	W
0	W	1	W
1	W	0	W
1	W	1	W
0	0	W	W
0	1	W	W
1	0	W	W
1	1	W	0

W	0	W	W
W	W	0	W
W	1	W	W
W	W	1	W
0	W	W	W
1	W	W	W

W	W	W	W

A	B	C	Z
0	0	0	A
0	0	1	0
0	1	0	A
0	1	1	0
1	0	0	A
1	0	1	0
1	1	0	0
1	1	1	0

W	0	0	W
W	0	1	0
W	1	0	W
W	1	1	0
0	W	0	W
0	W	1	0
1	W	0	W
1	W	1	0
0	0	W	W
0	1	W	W
1	0	W	W
1	1	W	0

W	0	W	W
W	W	0	W
W	1	W	W
W	W	1	0
0	W	W	W
1	W	W	W

W	W	W	W

A	B	C	Z
0	0	0	1
0	0	1	V
0	1	0	1
0	1	1	V
1	0	0	1
1	0	1	V
1	1	0	0
1	1	1	0

W	0	0	1
W	0	1	V
W	1	0	W
W	1	1	V
0	W	0	1
0	W	1	V
1	W	0	W
1	W	1	W
0	0	W	W
0	1	W	W
1	0	W	W
1	1	W	0

W	0	W	W
W	W	0	W
W	1	W	W
W	W	1	W
0	W	W	W
1	W	W	W

W	W	W	W

A	B	C	Z
0	0	0	1
0	0	1	0
0	1	0	A
0	1	1	0
1	0	0	1
1	0	1	0
1	1	0	V
1	1	1	0

W	0	0	1
W	0	1	0
W	1	0	W
W	1	1	0
0	W	0	W
0	W	1	0
1	W	0	W
1	W	1	0
0	0	W	W
0	1	W	W
1	0	W	W
1	1	W	W

W	0	W	W
W	W	0	W
W	1	W	W
W	W	1	0
0	W	W	W
1	W	W	W

W	W	W	W

A	B	C	Z
0	0	0	1
0	0	1	0
0	1	0	A
0	1	1	0
1	0	0	1
1	0	1	0
1	1	0	0
1	1	1	0

W	0	0	1
W	0	1	0
W	1	0	W
W	1	1	0
0	W	0	W
0	W	1	0
1	W	0	W
1	W	1	0
0	0	W	W
0	1	W	W
1	0	W	W
1	1	W	0

W	0	W	W
W	W	0	W
W	1	W	W
W	W	1	0
0	W	W	W
1	W	W	W

W	W	W	W

A	B	C	Z
0	0	0	1
0	0	1	0
0	1	0	1
0	1	1	0
1	0	0	1
1	0	1	0
1	1	0	V
1	1	1	0

W	0	0	1
W	0	1	0
W	1	0	W
W	1	1	0
0	W	0	1
0	W	1	0
1	W	0	W
1	W	1	0
0	0	W	W
0	1	W	W
1	0	W	W
1	1	W	W

W	0	W	W
W	W	0	W
W	1	W	W
W	W	1	0
0	W	W	W
1	W	W	W

W	W	W	W

N4*N3*N2*N1*A

N4-0*N3-1*N2-1*N1-0*A-1

NOR

AND

OR

XOR

N4N3N2N1A

N4-0N3-1N2-1N1-0A-1

A	B	C	D	Z
0	0	0	0	1
0	0	0	1	1
0	0	1	0	1
0	0	1	1	1
0	1	0	0	1
0	1	0	1	1
0	1	1	0	1
0	1	1	1	1
1	0	0	0	1
1	0	0	1	1
1	0	1	0	1
1	0	1	1	1
1	1	0	0	1
1	1	0	1	1
1	1	1	0	1
1	1	1	1	0
W	0	x	x	1
W	1	1	1	W

A	B	C	D	Z
0	0	0	0	1
0	0	0	1	1
0	0	1	0	1
0	0	1	1	1
0	1	0	0	1
0	1	0	1	1
0	1	1	0	1
0	1	1	1	A
1	0	0	0	1
1	0	0	1	1
1	0	1	0	1
1	0	1	1	1
1	1	0	0	1
1	1	0	1	1
1	1	1	0	1
1	1	1	1	0
x	W	0	x	1
x	W	1	1	W

A	B	C	D	Z
0	0	0	0	1
0	0	0	1	1
0	0	1	0	1
0	0	1	1	1
0	1	0	0	1
0	1	0	1	1
0	1	1	0	1
0	1	1	1	1
1	0	0	0	1
1	0	0	1	1
1	0	1	0	1
1	0	1	1	1
1	1	0	0	1
1	1	0	1	1
1	1	1	0	1
1	1	1	1	V
0	W	x	x	1
x	W	1	1	W

A	B	C	Z
W	0	0	1
W	0	1	0
W	1	0	W
W	1	1	0
0	W	0	1
0	W	1	0
1	W	0	W
1	W	1	0
0	0	W	W
0	1	W	W
1	0	W	W
1	1	W	0

W	0	W	W
W	W	0	W
W	1	W	W
W	W	1	0
0	W	W	W
1	W	W	W

W	W	W	W

A	B	C	Z
0	0	0	W
0	0	1	W
0	1	0	W
0	1	1	W
1	0	0	W
1	0	1	W
1	1	0	0
1	1	1	0

W	0	0	W
W	0	1	W
W	1	0	W
W	1	1	W
0	W	0	W
0	W	1	W
1	W	0	W
1	W	1	W
0	0	W	W
0	1	W	W
1	0	W	W
1	1	W	0

W	0	W	W
W	W	0	W
W	1	W	W
W	W	1	W
0	W	W	W
1	W	W	W

W	W	W	W

A	B	C	Z
0	0	0	A
0	0	1	0
0	1	0	A
0	1	1	0
1	0	0	A
1	0	1	0
1	1	0	0
1	1	1	0

W	0	0	W
W	0	1	0
W	1	0	W
W	1	1	0
0	W	0	W
0	W	1	0
1	W	0	W
1	W	1	0
0	0	W	W
0	1	W	W
1	0	W	W
1	1	W	0

W	0	W	W
W	W	0	W
W	1	W	W
W	W	1	0
0	W	W	W
1	W	W	W

W	W	W	W

A	B	C	Z
0	0	0	1
0	0	1	V
0	1	0	1
0	1	1	V
1	0	0	1
1	0	1	V
1	1	0	0
1	1	1	0

W	0	0	1
W	0	1	V
W	1	0	W
W	1	1	V
0	W	0	1
0	W	1	V
1	W	0	W
1	W	1	W
0	0	W	W
0	1	W	W
1	0	W	W
1	1	W	0

W	0	W	W
W	W	0	W
W	1	W	W
W	W	1	W
0	W	W	W
1	W	W	W

W	W	W	W

A	B	C	Z
0	0	0	1
0	0	1	0
0	1	0	A
0	1	1	0
1	0	0	1
1	0	1	0
1	1	0	V
1	1	1	0

W	0	0	1
W	0	1	0
W	1	0	W
W	1	1	0
0	W	0	W
0	W	1	0
1	W	0	W
1	W	1	0
0	0	W	W
0	1	W	W
1	0	W	W
1	1	W	W

W	0	W	W
W	W	0	W
W	1	W	W
W	W	1	0
0	W	W	W
1	W	W	W

W	W	W	W

A	B	C	Z
0	0	0	1
0	0	1	0
0	1	0	A
0	1	1	0
1	0	0	1
1	0	1	0
1	1	0	0
1	1	1	0

W	0	0	1
W	0	1	0
W	1	0	W
W	1	1	0
0	W	0	W
0	W	1	0
1	W	0	W
1	W	1	0
0	0	W	W
0	1	W	W
1	0	W	W
1	1	W	0

W	0	W	W
W	W	0	W
W	1	W	W
W	W	1	0
0	W	W	W
1	W	W	W

W	W	W	W

A	B	C	Z
0	0	0	1
0	0	1	0
0	1	0	1
0	1	1	0
1	0	0	1
1	0	1	0
1	1	0	V
1	1	1	0

W	0	0	1
W	0	1	0
W	1	0	W
W	1	1	0
0	W	0	1
0	W	1	0
1	W	0	W
1	W	1	0
0	0	W	W
0	1	W	W
1	0	W	W
1	1	W	W

W	0	W	W
W	W	0	W
W	1	W	W
W	W	1	0
0	W	W	W
1	W	W	W

W	W	W	W